Method and apparatus for reducing read disturb in memory
AssigneeMacronix International Co., Ltd.
InventorsChun Hsiung Hung, Shuo-Nan Hung, Tseng-Yi Liu
Life of this patent
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Abstract
Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.
Claims20
A memory, comprising:
- a plurality of memory cells arranged in series in a semiconductor body, the series having a first end and a second end, the plurality of memory cells having a threshold voltage in one of a first threshold voltage distribution associated with a first data value and a second threshold voltage distribution associated with a second data value, the first threshold voltage distribution having a first minimum and a first maximum and the second threshold voltage distribution having a second minimum and a second maximum, the first threshold voltage distribution being a lower voltage distribution than the second threshold voltage distribution, the plurality of memory cells including:
- a first set of two or more memory cells, memory cells in the first set of two or more memory cells, the threshold voltages in the first set of two or more memory cells representing copies of a same data value;
- a second set of two or more memory cells having the threshold voltage in a default threshold voltage distribution;
- a plurality of word lines, word lines in the plurality of word lines coupled to corresponding memory cells in the plurality of memory cells;
- and
- a control circuit coupled to the plurality of word lines,
- wherein the control circuit applies a read bias arrangement to the plurality of word lines to read a selected data value stored on the plurality of memory cells by measuring current flowing between the first end and the second end of the series, wherein the read bias arrangement applied to word lines of the plurality of word lines applies only word line voltages less than the second maximum of the second threshold voltage distribution.
A method of using a plurality of memory cells arranged in series in a semiconductor body, the series having a first end and a second end, the plurality including a first set of two or more memory cells, memory cells in the first set of two or more memory cells having a threshold voltage in one of a first threshold voltage distribution associated with a first data value and a second threshold voltage distribution associated with a second data value, the first threshold voltage distribution being a lower voltage distribution than the second threshold voltage distribution, the first threshold voltage distribution having a first minimum and a first maximum and the second threshold voltage distribution having a second minimum and a second maximum, the plurality including a second set of two or more memory cells having the threshold voltage in a default threshold voltage distribution comprising:
- applying a read bias arrangement to a first set of two or more word lines coupled to the first of two or more memory cells to read a selected data value stored on the first set of two or more memory cells by measuring current flowing between the first end and the second end of the series, wherein the read bias arrangement applied to word lines of the first set of two or more word lines applies only word line voltages less than the second maximum of the second threshold voltage distribution.
A memory, comprising:
- a plurality of memory cells arranged in series in a semiconductor body, the series having a first end and a second end, the plurality of memory cells having a threshold voltage in one of a first threshold voltage distribution associated with a first data value and a second threshold voltage distribution associated with a second data value, the first threshold voltage distribution having a first minimum and a first maximum and the second threshold voltage distribution having a second minimum and a second maximum, the first threshold voltage distribution being a lower voltage distribution than the second threshold voltage distribution, the plurality of memory cells including:
- a first set of two or more memory cells, memory cells in the first set of two or more memory cells programmed to store the threshold voltage in the second threshold voltage distribution, the threshold voltages in the first set of two or more memory cells representing copies of the second data value;
- a second set of two or more memory cells having the threshold voltage in a default threshold voltage distribution;
- a plurality of word lines, word lines in the plurality of word lines coupled to corresponding memory cells in the plurality of memory cells;
- and
- a control circuit coupled to the plurality of word lines,
- wherein the control circuit applies a read bias arrangement to the plurality of word lines to read a selected data value stored on the plurality of memory cells by measuring current flowing between the first end and the second end of the series, wherein the read bias arrangement applied to word lines of the plurality of word lines applies only word line voltages less than the second maximum of the second threshold voltage distribution.
Dependencies are inferred from the claim text.