Reference cell circuit and variable resistance nonvolatile memory device including the same

A variable resistance nonvolatile memory device comprising:

• a memory cell array which includes a plurality of memory cells arranged in rows and columns, each of the memory cells including a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range;
• a reference circuit which includes at least one reference cell circuit, and generates a reference level for determining a resistance state of each of the memory cells with reference to a resistance value of a reference cell connected to an output terminal of the at least one reference cell circuit;
• and
• a read circuit which determines whether each memory cell is in the low resistance state or in the high resistance state by comparing a signal level obtained from the memory cell with the reference level generated by the reference circuit,
• wherein each of the at least one reference cell circuit includes:
• a first reference cell and a second reference cell each of which includes a variable resistance element which reversibly changes between the low resistance state and the high resistance state according to an application of an electric signal;
• a comparator which compares a resistance value of the first reference cell with a resistance value of the second reference cell;
• a control circuit;
• an application circuit which applies an electric signal to a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit, the electric signal being for setting the selected reference cell to a target state which is one of the low resistance state and the high resistance state;
• and
• an output circuit which electrically connects, to an output terminal, a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit,
• wherein the control circuit executes a comparison operation and a write operation one or more times, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to a target resistance value that is a lower limit value or an upper limit value of the target state, the comparison operation causing the comparator to perform the comparison, and the write operation causing the application circuit to apply the electric signal to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from the target resistance value according to each result of the comparison by the comparator, and
• after the write operation, the control circuit executes an output operation which causes the output circuit to electrically connect, to the output terminal, a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value closer to the target resistance value according to a result of the comparison by the comparator.

A variable resistance nonvolatile memory device comprising:

• a memory cell array including a plurality of memory cells arranged in rows and columns, each of the memory cells including a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range;
• a refresh command circuit which includes a reference cell circuit, and outputs a refresh command signal when a resistance value of a reference cell connected to an output terminal of the reference cell circuit becomes a predetermined value;
• and
• a control circuit which performs a read operation and then a refresh operation on at least a part of the memory cells in the memory cell array when the refresh command signal is output, the read operation being for reading data from the part of the memory cells, and the refresh operation being for rewriting the read data to the part of the memory cells,
• wherein the reference cell circuit includes:
• a first reference cell and a second reference cell each of which includes a variable resistance element which reversibly changes between the low resistance state and the high resistance state according to an application of an electric signal;
• a comparator which compares a resistance value of the first reference cell with a resistance value of the second reference cell;
• a control circuit;
• an application circuit which applies an electric signal to a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit, the electric signal being for setting the selected reference cell to a target state which is one of the low resistance state and the high resistance state;
• and
• an output circuit which electrically connects, to an output terminal, a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit,
• wherein the control circuit executes a comparison operation and a write operation one or more times, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to a target resistance value that is a lower limit value or an upper limit value of the target state, the comparison operation causing the comparator to perform the comparison, and the write operation causing the application circuit to apply the electric signal to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from the target resistance value according to each result of the comparison by the comparator, and
• after the write operation, the control circuit executes an output operation which causes the output circuit to electrically connect, to the output terminal, a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value closer to the target resistance value according to a result of the comparison by the comparator.

A method for setting a reference cell circuit including a first reference cell and a second reference cell each of which includes a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range, and the method comprising:

• applying an electric signal one or more times to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from a target resistance value according to each result of a comparison between a resistance value of the first reference cell and a resistance value of the second reference cell, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to the target resistance value, the target resistance value being a lower limit value or an upper limit value of a target state that is one of the low resistance state and the high resistance state, and the electric signal being for setting the reference cell to the target state;
• and
• after the applying, electrically connecting, to an output terminal, one of the first reference cell and the second reference cell which has a resistance value closer to the target resistance value according to a result of a comparison between the resistance value of the first reference cell and the resistance value of the second reference cell.

A method for controlling a variable resistance nonvolatile memory device including a plurality of memory cells, a first reference cell and a second reference cell, each of which includes a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range, the memory cells being arranged in rows and columns to form a memory cell array, the first reference cell and the reference cell forming a reference cell circuit, and the method comprising:

• applying an electric signal one or more times to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from a target resistance value according to each result of a comparison between a resistance value of the first reference cell and a resistance value of the second reference cell, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to the target resistance value, the target resistance value being a lower limit value or an upper limit value of a target state that is one of the low resistance state and the high resistance state, and the electric signal being for setting the reference cell to the target state;
• after the applying, electrically connecting, to an output terminal, one of the first reference cell and the second reference cell which has a resistance value closer to the target resistance value according to a result of a comparison between the resistance value of the first reference cell and the resistance value of the second reference cell;
• generating a reference level for determining a resistance state of each of the memory cells, with reference to a resistance value of a reference cell connected to an output terminal of the reference cell circuit;
• and
• determining whether each memory cell is in the low resistance state or in the high resistance state by comparing a signal level obtained from the memory cell with the generated reference level.

A method for controlling a variable resistance nonvolatile memory device including a plurality of memory cells, a first reference cell and a second reference cell, each of which includes a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range, the memory cells being arranged in rows and columns to form a memory cell array, the first reference cell and the reference cell forming a reference cell circuit, and the method comprising:

• applying an electric signal one or more times to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from a target resistance value according to each result of a comparison between a resistance value of the first reference cell and a resistance value of the second reference cell, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to the target resistance value, the target resistance value being a lower limit value or an upper limit value of a target state that is one of the low resistance state and the high resistance state, and the electric signal being for setting the reference cell to the target state;
• after the applying, electrically connecting, to an output terminal, one of the first reference cell and the second reference cell which has a resistance value closer to the target resistance value according to a result of a comparison between the resistance value of the first reference cell and the resistance value of the second reference cell;
• outputting a refresh command signal when a resistance value of a reference cell connected to an output terminal of the reference cell circuit becomes a predetermined value;
• and
• performing a read operation and then a refresh operation on at least a part of the memory cells in the memory cell array when the refresh command signal is output, the read operation being for reading data from the part of the memory cells, and the refresh operation being for rewriting the read data to the part of the memory cells.