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US 8,787,065 B2Granted
Apparatuses and methods for determining stability of a memory cell
AssigneeMicron Technology, Inc.
InventorAlessandro Torsi
Life of this patent
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Abstract
Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state.
Claims43
A method for determining stability of a resistance variable memory cell, the method comprising:
- providing a pulse to the resistance variable memory cell to place the resistance variable memory cell in a target state;
- determining a resistance of the resistance variable memory cell after providing the pulse;
- if the resistance of the resistance variable memory cell indicates the resistance variable memory cell is in the target state, stressing the resistance variable memory cell by providing another pulse to the resistance variable memory cell;
- determining a resistance of the resistance variable memory cell after stressing the resistance variable memory cell;
- and
- if the resistance of the resistance variable memory cell indicates the resistance variable memory cell is still in the target state, determining that the resistance variable memory cell is stable.
3 more elements
A method for determining stability a resistance variable memory cell, the method comprising:
- providing a first series of pulses to the resistance variable memory cell to place the resistance variable memory cell in a first target state;
- if the resistance variable memory cell is determined to be in the first target state, providing another pulse to the resistance variable memory cell to stress the resistance variable memory cell in the first target state;
- determining the resistance of the resistance variable memory cell after providing the another pulse;
- and
- if the resistance of the resistance variable memory cell indicates the resistance variable memory cell is still in the first target state:
- determining the resistance variable memory cell is stable in the first target state;
- and
- providing a second series of pulses to the resistance variable memory cell to place the resistance variable memory cell in a second target state.
5 more elements
A method comprising:
- determining whether a resistance variable memory cell is in a target state;
- after determining that the resistance variable memory cell is in the target state, determining whether the resistance variable memory cell is in a stable state by:
- stressing the resistance variable memory cell;
- and
- determining whether the resistance variable memory cell is still in the target state after stressing the resistance variable memory cell;
- and
- if the resistance variable memory cell is determined to be in a stable state, determining the resistance variable memory cell is a stable resistance variable memory cell.
4 more elements
An apparatus comprising:
- a resistance variable memory cell;
- and
- a controller configured to selectively cause the resistance variable memory cell to be set and reset, wherein the controller is configured to cause a first pulse to be provided to the resistance variable memory cell to place the resistance variable memory cell in a first target state, after the resistance variable memory cell is verified to be in the first target state, the controller is further configured to cause a first test pulse to be provided to the resistance variable memory cell to determine whether the resistance variable memory cell is stable in the first target state based on a resistance of the resistance variable memory cell, wherein the controller is further configured to cause a second test pulse to be provided to the resistance variable memory cell to place the resistance variable memory cell in a second target state, after the resistance variable memory cell is verified to be in the second target state the controller is further configured to cause a second test pulse to be provided to the resistance variable memory cell to determine whether the resistance variable memory cell is stable in the second target state based on a resistance of the resistance variable memory cell.
An apparatus comprising:
- a resistance variable memory cell;
- and
- a controller configured to cause a pulse to be provided to the resistance variable memory to place the resistance variable memory cell in a target state, after the resistance variable memory cell is verified to be in the target state, the controller is further configured to cause the resistance variable memory cell to be intentionally stressed to determine the resistance variable memory cell stable by verifying the resistance variable memory cell remains in the target state and unstable if the resistance variable memory cell is in a state other than the target state, wherein the controller is further configured to cause another pulse to be provided to the resistance variable memory cell if the resistance variable memory cell is determined to be unstable.
An apparatus comprising:
- a resistance variable memory cell;
- and
- a controller configured to:
- determine whether the resistance variable memory cell is in a target state;
- after determining that the resistance variable memory cell is in the target state:
- provide a pulse to the resistance variable memory cell to stress the resistance variable memory cell;
- and
- determine whether the resistance variable memory cell is in a stable state based on the resistance variable memory cell remaining in the target state after provision of the pulse;
- and
- if the resistance variable memory cell is determined to be in a stable state, determine the resistance variable memory cell is a stable resistance variable memory cell.
7 more elements
An apparatus comprising:
- a resistance variable memory cell;
- and
- a controller configured to:
- cause a pulse to be provided to the resistance variable memory cell to place the resistance variable memory cell in a target state;
- determine a resistance of the resistance variable memory cell after the pulse is provided;
- if the resistance of the resistance variable memory cell indicates the resistance variable memory cell is in the target state, cause the resistance variable memory cell to be intentionally stressed at least in part by causing a another pulse to be provided to the resistance variable memory cell;
- determine the resistance of the resistance variable memory cell after the resistance variable memory cell is intentionally stressed;
- and
- if the resistance of the resistance variable memory cell indicates the resistance variable memory cell is still in the target state, provide an indication the resistance variable memory cell is a stable resistance variable memory cell.
6 more elements
Dependencies are inferred from the claim text.