US 8,787,061 B2Granted

Semiconductor memory device

AssigneeKabushiki Kaisha Toshiba

InventorFumihiro Kono

Life of this patent

Estimating the term…

Loading patent…

Abstract

According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

Claims18

Dependent claims

A semiconductor memory device, comprising:

a semiconductor substrate;
memory units including memory cells that are stacked above the semiconductor substrate, the memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adj acent to the first memory unit in a second direction crossing the first direction, the first memory unit including a first memory cell, the second memory unit including a second memory cell, the third memory unit including a third memory cell, a gate of the first memory cell being electrically connected to a gate of the second memory cell;
and
bit lines disposed above the memory units, the bit lines extending in a third direction, the bit lines including a first bit line and a second bit line, the second bit line being adjacent to the first bit line in the first direction, the third direction being different from both the first direction and the second direction, and the third direction being parallel to the semiconductor substrate, wherein
a first pitch is larger than a second pitch, the first pitch being a distance between the first memory unit and the second memory unit, the second pitch being a distance between the first bit line and the second bit line.

2 more elements

A semiconductor memory device, comprising:

a semiconductor substrate;
memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adjacent to the first memory unit in a second direction crossing the first direction, the first memory unit including a first memory cell, the second memory unit including a second memory cell, the third memory unit including a third memory cell, a gate of the first memory cell being electrically connected to a gate of the second memory cell;
and
bit lines disposed above the memory units, the bit lines extending in a third direction, the third direction being different from both the first direction and the second direction, the third direction being parallel to the semiconductor substrate,
wherein a distance between the first memory unit and the third memory unit in the third direction is smaller than a distance between the first memory unit and the second memory unit in the first direction.

2 more elements

A semiconductor memory device, comprising:

a semiconductor substrate;
memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adjacent to the first memory unit in a second direction crossing the first direction, the first memory unit including a first memory cell, the second memory unit including a second memory cell, the third memory unit including a third memory cell, and a gate of the first memory cell being electrically connected to a gate of the second memory cell;
and
bit lines disposed above the memory units, the bit lines extending in a third direction, the third direction being different from both the first direction and the second direction, the third direction being parallel to the semiconductor substrate,
wherein the memory units comprise:
a semiconductor body extending in a direction perpendicular to the semiconductor substrate;
a charge storage layer surrounding the semiconductor body;
and
a word line surrounding the charge storage layer, and
a length of the word line in the third direction is smaller than a sum of two closet distances in the third direction from sides of the semiconductor bodies to both ends of the word line, two diameter's width of the semiconductor body, and a spacing between the semiconductor body of the first memory cell and the semiconductor body of the third memory cell.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/524,750Filed 15 Jun 2012
Priority: JP 2011-13509317 Jun 2011
Published: US 2012/0320652 A120 Dec 2012
Granted: 22 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits

Family

US 2012/0320652 A1Pre-grant publication · published 20 Dec 2012
US 8,787,061 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key