Method and apparatus for optimizing driver load in a memory package

A memory package, comprising:

• a plurality of input/output terminals via which the memory package communicates data and control/address signals with one or more external devices;
• a plurality of array dies arranged in a stack, including a first group of array dies and a second group of at least one array die;
• at least a first die interconnect and a second die interconnect, the first die interconnect in electrical communication with the first group of array dies and not in electrical communication with the second group of at least one array die, the second die interconnect in electrical communication with the second group of at least one array die and not in electrical communication with the first group of array dies;
• and
• a control die comprising at least a first data conduit between the first die interconnect and a first terminal of the plurality of input/output terminals, at least a second data conduit between the second die interconnect and the first terminal, and chip select conduits for providing chip select signals to respective array dies;
• wherein the control die further comprises a control circuit to control respective states of the first data conduit and the second data conduit to drive a data signal to an array die selected by at least one of the chip-select signals.

A method for optimizing load in a memory package comprising a plurality of array dies arranged in a stack and including a first group of array dies and a second group of at least one array die, at least a first die interconnect and a second die interconnect, a control die, and a plurality of input/output terminals via which the memory package communicates data and control/address signals with one or more external devices, the method comprising:

• receiving a data signal at a first terminal of the plurality of input/output terminals;
• receiving control signals at second terminals of the plurality of input/output terminals;
• providing chip select signals to respective array dies through the control die, the chip select signals being related to at least some of the control signals;
• and
• selecting one of a first driver and a second driver in the control die to drive the data signal via a corresponding one of the first die interconnect and the second die interconnect to an array die selected by at least one of the chip select signals, the first die interconnect in electrical communication with the first group of array dies and not in electrical communication with the second group of at least one array die, the second die interconnect in electrical communication with the second group of at least one array die and not in electrical communication with the first group of array dies.

A memory module operable via a memory control hub, comprising:

• a register device configured to receive command/address signals from the memory control hub and to generate control signals;
• and
• a plurality of DRAM packages, each DRAM package comprising:
• a plurality of data terminals via which the DRAM package communicates data with the memory control hub, and a plurality of control terminals to receive the control signals;
• a plurality of array dies arranged in a stack, including a first group of array dies and a second group of at least one array die;
• at least a first die interconnect and a second die interconnect, the first die interconnect in electrical communication with the first group of array dies and not in electrical communication with the second group of at least one array die, the second die interconnect in electrical communication with the second group of at least one array die and not in electrical communication with the first group of array dies;
• and
• a control die comprising at least a first data conduit between the first die interconnect and a first data terminal of the plurality of data terminals, at least a second data conduit between the second die interconnect and the first data terminal, and chip select conduits for providing chip select signals to respective array dies, the chip select signals being related to at least some of the control signals;
• wherein the control die further comprises a control circuit to control respective states of the first data conduit and the second data conduit to drive a data signal to an array die selected by at least one of the chip-select signals.