Back to results
US 8,787,058 B2Granted
Selectable multi-way comparator
AssigneeAdvanced Micro Devices, Inc.
InventorsGanesh Venkataramanan, Michael G. Butler, James Vinh
Life of this patent
Estimating the term…
Abstract
A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is provided to the group of comparators, the match value corresponding to a binary value pair to be compared with the binary value stored in the pair of CAM elements. A positive match result value is output from a selected group of comparators via an output line in response to the comparison value matching the match value.
Claims12
A content addressable memory (CAM), comprising:
- a plurality of pairs of CAM elements, each pair of CAM elements storing binary values;
- a plurality of sets of decoders, each set of decoders connected to one pair of CAM elements and configured to provide a comparison value;
- a plurality of sets of match lines, each set of match lines configured to provide a match value on only one of the match lines;
- a plurality of sets of comparators, wherein the comparison value is supplied to one of the sets of comparators and the match value is supplied to the one set of comparators, the one set of comparators configured to compare the comparison value to the match value;
- a multiplexor connected to each of the sets of comparators, the multiplexor having two or more input lines and configured to select one of the sets of comparators based on values on the input lines;
- and
- a single output line connected to each of the comparators, wherein a positive match result value is output on the output line responsive to a comparator indicating a match between the comparison value and the match value.
4 more elements
A scheduler, comprising:
- a content addressable memory (CAM), including:
- a plurality of pairs of CAM elements, each pair of CAM elements storing binary values;
- a plurality of sets of decoders, each set of decoders connected to one pair of CAM elements and configured to provide a comparison value;
- a plurality of sets of match lines, each set of match lines configured to provide a match value on only one of the match lines;
- a plurality of sets of comparators, wherein the comparison value is supplied to one of the sets of comparators and the match value is supplied to the one set of comparators, the one set of comparators configured to compare the comparison value to the match value;
- a multiplexor connected to each of the sets of comparators, the multiplexor having two or more input lines and configured to select one of the sets of comparators based on values on the input lines;
- and
- a single output line connected to each of the comparators, wherein a positive match result value is output on the output line responsive to a comparator indicating a match between the comparison value and the match value.
5 more elements
A processor core, comprising:
- a content addressable memory (CAM), including:
- a plurality of pairs of CAM elements, each pair of CAM elements storing binary values;
- a plurality of sets of decoders, each set of decoders connected to one pair of CAM elements and configured to provide a comparison value;
- a plurality of sets of match lines, each set of match lines configured to provide a match value on only one of the match lines;
- a plurality of sets of comparators, wherein the comparison value is supplied to one of the sets of comparators and the match value is supplied to the one set of comparators, the one set of comparators configured to compare the comparison value to the match value;
- a multiplexor connected to each of the sets of comparators, the multiplexor having two or more input lines and configured to select one of the sets of comparators based on values on the input lines;
- and
- a single output line connected to each of the comparators, wherein a positive match result value is output on the output line responsive to a comparator indicating a match between the comparison value and the match value.
5 more elements
A processor, comprising:
- a content addressable memory (CAM), including:
- a plurality of pairs of CAM elements, each pair of CAM elements storing binary values;
- a plurality of sets of decoders, each set of decoders connected to one pair of CAM elements and configured to provide a comparison value;
- a plurality of sets of match lines, each set of match lines configured to provide a match value on only one of the match lines;
- a plurality of sets of comparators, wherein the comparison value is supplied to one of the sets of comparators and the match value is supplied to the one set of comparators, the one set of comparators configured to compare the comparison value to the match value;
- a multiplexor connected to each of the sets of comparators, the multiplexor having two or more input lines and configured to select one of the sets of comparators based on values on the input lines;
- and
- a single output line connected to each of the comparators, wherein a positive match result value is output on the output line responsive to a comparator indicating a match between the comparison value and the match value.
5 more elements
A system, comprising:
- a memory;
- and
- a content addressable memory (CAM), including:
- a plurality of pairs of CAM elements, each pair of CAM elements storing binary values;
- a plurality of sets of decoders, each set of decoders connected to one pair of CAM elements and configured to provide a comparison value;
- a plurality of sets of match lines, each set of match lines configured to provide a match value on only one of the match lines;
- a plurality of sets of comparators, wherein the comparison value is supplied to one of the sets of comparators and the match value is supplied to the one set of comparators, the one set of comparators configured to compare the comparison value to the match value;
- a multiplexor connected to each of the sets of comparators, the multiplexor having two or more input lines and configured to select one of the sets of comparators based on values on the input lines;
- and
- a single output line connected to each of the comparators, wherein a positive match result value is output on the output line responsive to a comparator indicating a match between the comparison value and the match value.
7 more elements
Dependencies are inferred from the claim text.