US 8,786,794 B2Granted

Semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsYoshinari Higaki, Masayuki Sakakura, Shunpei Yamazaki

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Abstract

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

Claims12

Dependent claims

A semiconductor device comprising:

a gate electrode over a substrate;
a gate insulating layer over the gate electrode;
a semiconductor layer over the gate insulating layer;
and
a source electrode and a drain electrode, over the semiconductor layer,
wherein one of the source electrode and the drain electrode is electrically connected to the semiconductor layer, and has a first electrode layer and a second electrode layer,
wherein the second electrode layer is formed on the first electrode layer,
wherein the first electrode layer comprises titanium,
wherein the second electrode layer comprises aluminum,
wherein a first width of the first electrode layer is larger than a second width of the second electrode layer,
wherein an upper surface of the second electrode layer is in contact with an insulating layer,
wherein the first electrode layer is in contact with a pixel electrode,
wherein the semiconductor layer comprises an amorphous silicon, and
wherein the pixel electrode comprises an ITO.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/967,645Filed 15 Aug 2013 · continuation
Priority: JP 2004-26767315 Sep 2004
Published: US 2013/0328050 A112 Dec 2013
Granted: 22 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 30/6732
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: bottom-gate only TFTs
H10D 30/67
Insulated-gate field-effect transistors [IGFET]: thin-film transistors [TFT]
H10D 30/6729
Thin-film transistors [TFT]: characterised by the electrodes
H10D 30/6737
Characterised by the electrodes: characterised by the electrode materials

Family

PCT/JP2005/017223Parent of this continuation · filed 13 Sep 2005
Application12/978,844Parent of this continuation · filed 27 Dec 2010
US 7,859,606 B2Parent of this continuation · filed 28 Dec 2010
US 2013/0328050 A1Pre-grant publication · published 12 Dec 2013
US 8,514,341 B2Parent of this continuation
Application10/576,177Parent of this continuation
US 2008/0136989 A1Published application
US 2011/0140120 A1Published application
US 8,786,794 B2This patent

From the US filing history. Foreign family members aren’t listed.

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