Display device and driving method thereof

A method for driving a display device comprising a driver circuit portion and a pixel portion comprising n (n is a natural number) pixels, the driver circuit portion comprising a first driver circuit and a second driver circuit, wherein each of the n pixels comprises a transistor, and wherein a channel formation region of the transistor comprises an oxide semiconductor layer, comprising the step of:

• performing operation N (N is a natural number) times in a still image display mode for displaying a still image in the pixel portion, the operation comprising:
• supplying a first driving signal and a first power supply voltage to the first driver circuit;
• supplying a second driving signal and a second power supply voltage to the second driver circuit;
• supplying a scan signal to the n pixels from the first driver circuit;
• supplying an image signal to the n pixels from the second driver circuit;
• stopping supply of the second driving signal and the second power supply voltage to the second driver circuit;
• and
• holding an image of the pixel portion based on the image signal as the still image,
• wherein in the case where N is greater than or equal to 2, a K-th (K is a natural number greater than or equal to 2 and less than or equal to N) period of stopping supply of the second driving signal and the second power supply voltage to the second driver circuit is set longer than a (K−1)-th period of stopping supply of the second driving signal and the second power supply voltage to the second driver circuit, and
• wherein an interval between the K-th period of supplying the image signal to the n pixels and the (K−1)-th period of supplying the image signal is 10 seconds or longer.

A display device comprising:

• a CPU supplied with an operation signal;
• a display control circuit;
• a first driver circuit;
• and
• a second driver circuit;
• and
• n (n is a natural number) pixels,
• wherein the CPU is configured to generate a first control signal and a second control signal in accordance with the operation signal, and the CPU is configured to supply the first control signal and the second control signal to the display control circuit,
• wherein the display control circuit is configured to supply a first start signal, a first clock signal and power supply voltage to the first driver circuit in accordance with the first control signal, and the display control circuit is configured to supply a second start signal, a second clock signal and power supply voltage to the second driver circuit in accordance with the second control signal,
• wherein the first driver circuit is configured to supply a scan signal to the n pixels,
• wherein the second driver circuit is configured to supply an image signal to the n pixels, and
• wherein the CPU comprises:
• a counting circuit;
• a latch circuit;
• an arithmetic circuit;
• and
• an output circuit,
• wherein the counting circuit is configured to count the number of pulses of a reference clock signal in each period set in accordance with the operation signal and the counting circuit is configured to supply data of counted value to the latch circuit in each period as a signal,
• wherein the latch circuit is configured to supply the data of counted value to the arithmetic circuit after holding the data of counted value for a certain period,
• wherein the arithmetic circuit is configured to generate signals in accordance with the data of counted value and the arithmetic circuit is configured to supply the signals to the output circuit,
• wherein the output circuit is configured to adjust and supply the signals to the display control circuit as the first control signal and the second control signal, and
• wherein the n pixels are controlled in accordance with the scan signal and the image signal, and
• wherein each of the n pixels comprises a transistor, and
• wherein a channel formation region of the transistor comprises an oxide semiconductor layer.