Liquid crystal display having line drivers with reduced need for wide bandwidth switching

A liquid crystal display comprising:

• a substrate;
• a plurality of gate lines formed on the substrate;
• a plurality of data lines crossing the gate lines;
• a plurality of thin film transistors connected to the gate lines and the data lines;
• a plurality of pixel electrodes connected to the thin film transistors;
• and
• at least three gate drivers each exclusively connected to a respective subset of the gate lines, the at least three gate drivers including a first gate driver, a second gate driver, and a third gate driver,
• wherein the first gate driver includes a first portion disposed on a first side of the liquid crystal display and a second portion disposed on a second side of the liquid crystal display, the second side being opposite to the first side,
• wherein the second gate driver includes a third portion disposed on the first side of the liquid crystal display and a fourth portion disposed on the second side of the liquid crystal display,
• wherein the third gate driver includes a fifth portion disposed on the first side of the liquid crystal display and a sixth portion disposed on the second side of the liquid crystal display,
• wherein the first portion and the second portion of the first gate driver are electrically connected to a first gate line, the third portion and the fourth portion of the second gate driver are electrically connected to a second gate line, and the fifth portion and the sixth portion of the third gate driver are electrically connected to a third gate line,
• wherein the first portion and the second portion of the first gate driver are further electrically connected to a fourth gate line, the third portion and the fourth portion of the second gate driver are further electrically connected to a fifth gate line, and the fifth portion and the sixth portion of the third gate driver are further electrically connected to a sixth gate line,
• wherein the second gate line and the third gate line are disposed between the first gate line and the fourth gate line in a layout view of the liquid crystal display, and
• wherein the fifth gate line is disposed between the fourth gate line and the sixth gate line in the layout view of the liquid crystal display,
• wherein the gate lines are supplied with gate signals including a gate-on voltage and a gate-off voltage, and the gate-on voltage is maintained for 3 horizontal periods.