US 8,786,533 B2Granted

Pulse output circuit, shift register and display device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsMunehiro Azami, Shou Nagao, Yoshifumi Tanada

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Abstract

A pulse is input to first and second TFTs to turn ON the first and second TFTs so that the potential of a node a rises. When the potential of the node a reaches (VDD−VthN), the node α enters a floating state. Accordingly, a third TFT then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the third TFT further rises due to an operation of capacitance as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the third TFT.

Claims17

Dependent claims

A display device comprising:

a substrate;
a driver circuit over the substrate;
and
a pixel over the substrate, and electrically connected to the driver circuit,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,
wherein the pixel comprises a seventh transistor and a display element,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor have a same conductivity type,
wherein a gate of the first transistor is electrically connected to a first input terminal,
wherein a gate of the second transistor is electrically connected to a second input terminal,
wherein a gate of the third transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to one of source and drain of the first transistor,
wherein the gate of the fifth transistor is electrically connected to one of source and drain of the second transistor,
wherein a gate of the sixth transistor is electrically connected to one of source and drain of the fourth transistor,
wherein the gate of the sixth transistor is electrically connected to one of source and drain of the third transistor,
wherein a first wiring is electrically connected to the other of source and drain of the first transistor,
wherein a second wiring is electrically connected to the other of source and drain of the second transistor,
wherein the second wiring is electrically connected to the other of source and drain of the fourth transistor,
wherein a wiring for supplying a clock signal is electrically connected to one of source and drain of the fifth transistor,
wherein an output terminal is electrically connected to the other of source and drain of the fifth transistor,
wherein the output terminal is electrically connected to one of source and drain of the sixth transistor, and
wherein the other of source and drain of the sixth transistor is electrically connected to the second wiring.

19 more elements

A semiconductor device comprising:

a substrate;
and
a driver circuit over the substrate,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor have a same conductivity type,
wherein a gate of the first transistor is electrically connected to a first input terminal,
wherein a gate of the second transistor is electrically connected to a second input terminal,
wherein a gate of the third transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to one of source and drain of the first transistor,
wherein the gate of the fifth transistor is electrically connected to one of source and drain of the second transistor,
wherein a gate of the sixth transistor is electrically connected to one of source and drain of the fourth transistor,
wherein the gate of the sixth transistor is electrically connected to one of source and drain of the third transistor,
wherein a first wiring is electrically connected to the other of source and drain of the first transistor,
wherein a second wiring is electrically connected to the other of source and drain of the second transistor,
wherein the second wiring is electrically connected to the other of source and drain of the fourth transistor,
wherein a wiring for supplying a clock signal is electrically connected to one of source and drain of the fifth transistor,
wherein an output terminal is electrically connected to the other of source and drain of the fifth transistor,
wherein the output terminal is electrically connected to one of source and drain of the sixth transistor, and
wherein the other of source and drain of the sixth transistor is electrically connected to the second wiring.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/604,709Filed 6 Sep 2012 · continuation
Priority: JP 2001-14134711 May 2001
Published: US 2013/0057161 A17 Mar 2013
Granted: 22 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
G02F 1/13306
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements: circuit arrangements or driving methods for the control of…
G02F 1/1333
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements: constructional arrangements; Manufacturing methods
G09G 3/36
By control of light from an independent source: using liquid crystals

Family

Application10/127,600Parent of this continuation · filed 23 Apr 2002
Application11/420,404Parent of this continuation · filed 25 May 2006
US 7,057,598 B2Parent of this continuation · filed 6 Jun 2006
Application12/575,642Parent of this continuation · filed 8 Oct 2009
US 7,710,384 B2Parent of this continuation · filed 4 May 2010
US 2013/0057161 A1Pre-grant publication · published 7 Mar 2013
US 8,264,445 B2Parent of this continuation
US 2002/0167026 A1Published application
US 2006/0202940 A1Published application
US 2010/0073348 A1Published application
US 8,665,197 B2Related patent
US 8,786,533 B2This patent

From the US filing history. Foreign family members aren’t listed.

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