US 8,786,483 B1 · Use of a DLL to optimize an ADC performance

Abstract

Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.

Claims20

Dependent claims

An integrated circuit comprising:

a successive approximation register (SAR) analog-to-digital converter (ADC) to convert an analog input signal into a digital signal;
a SAR timer comprising a pair of programmable timing circuits, a first timing circuit to delay an amplification phase of the SAR ADC during operation and a second timing circuit to delay a latch phase of the SAR ADC during operation;
a reference circuit system to act as a timing reference for the programmable timing circuits and calibrate each programmable timing circuit if they are operating faster or slower than expected.

Dependencies are inferred from the claim text.

Use of a DLL to optimize an ADC performance

Life of this patent

Use of a DLL to optimize an ADC performance

Life of this patent

Abstract

Claims20