Digital analog converter circuit, digital driver and display device

A digital to analog conversion circuit comprising

• a decoder that receives a reference voltage ensemble including a plurality of reference voltages, different each other and m-bit digital data, where m is a predetermined positive integer, and that selects first and second voltages from said reference voltage ensemble, in accordance with said m-bit digital data;
• and
• an interpolation circuit that receives said first and second voltages selected by said decoder and interpolates said first and second voltages with an interpolation ratio of 1:1 to generate an interpolated voltage level;
• wherein said plurality of reference voltages of said reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is an integer which is a power of 2 and includes 1, and z is an integer which is not less than 5 and is represented by a power of 2 plus one,
• said plurality of reference voltages of said reference voltage ensemble being mapped in a two-dimensional array with (z×S+1) rows and h columns, h being an integer not less than 2,
• said first to (z×S+1)th reference voltage groups being allocated respectively to first to (z×S+1)th rows of said two-dimensional array, and k-th reference voltage in each of said reference voltage groups, where k is an integer not less then 1 and not greater than h, being allocated to k-th column of said two-dimensional array,
• an array element of an i-th row and j-th column of said two-dimensional array, where i is an integer not less than 1 and not greater than (z×S+1), and j is an integer not less than 1 and not greater than h, corresponding to {(j−1)×(z×S+i)}th reference voltage,
• wherein said decoder includes:
• first to (z×S+1)th sub-decoders which are provided in association with said first to (z×S+1)th reference voltage groups, respectively, receive a first bit group of said m-bit digital data in common and receive said reference voltages of said respective first to (z×S+1)th reference voltage groups, and which select, from among said received reference voltages of said respective first to (z×S+1)th reference voltage groups, respective reference voltages allocated in common to a column of said two-dimensional array, said column corresponding to a value of said first bit group of said m-bit digital data;
• and
• a (z×S+1) input and two output type sub-decoder that receives a second bit group of said m-bit digital data and receives outputs of said first to (z×S+1)th sub-decoders and that selects said first and second voltages out of said reference voltages which are selected by said first to (z×S+1)th sub-decoders in accordance with a value of said second bit group of said m-bit digital data, wherein
• said reference voltage ensemble includes reference voltages associated with ones of a plurality of voltage levels that are able to be output from said interpolation circuit,
• with an A-th voltage level being as a reference, said reference voltage ensemble including, regarding said z and an index number N,
• z number of reference voltages which are associated with
• (4×(z−1)×N+A)th voltage level;
• (4×(z−1)×N+A+2)th voltage level;
• reference voltages, each sequentially spaced apart by four unit levels from said (4×(z−1)×N+A+2)th voltage level, namely
• a (4×(z−1)×N+A+6)th voltage level,
• a (4×(z−1)×N+A+10)th voltage level, and up to
• a (4×(z−1)(N+1)+(A−2)th voltage level;
• said index number N being an integer value from 0 to (N′−1), where N′ being a predetermined integer not less than 1, said reference voltage ensemble further includes in total a reference voltage associated with the (4×(z−1)×N′+A)th voltage level, such that said reference voltage ensemble includes in total (z×N′+1) reference voltages, for (4×(z−1)×N′+1) voltage levels, that range from the A-th voltage level to the (4×(z−1)×N′+A)th voltage level and that are able to be output by said interpolation circuit.