Circuit for implementing a continuous-time deglitching technique for digital analog converters

A circuit, comprising:

• a digital-to-analog converter (DAC) having a differential output;
• an operational amplifier having an inverting input coupled to a first output of the differential output and a non-inverting input coupled to a second output of the differential output, wherein the first output is a non-inverting output of the DAC and the second output is an inverting output of the DAC;
• and
• a transistor coupled to the second output and the output of the operational amplifier,
• wherein the operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output and, the transistor is an NMOS (n-type Metal Oxide Semiconductor) transistor having a drain coupled to the second output, and a source coupled to a ground potential.

A circuit, comprising:

• a digital-to-analog converter (DAC) having a differential output, wherein the DAC is configured to receive an N-bit digital input signal and generate a first output of the differential output and a second output of the differential output based on the N-bit digital input signal;
• an operational amplifier having an inverting input coupled to the first output and a non-inverting input coupled to the second output;
• and
• a transistor coupled to the second output and the output of the operational amplifier, wherein the operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output, and a current supplied to the first output is proportional to the N-bit digital input signal, and a current supplied to the second output is proportional to an inverted version of the N-bit digital input signal.

A circuit, comprising:

• a digital-to-analog converter (DAC) having a differential output, wherein the DAC comprises a number of unit cells, and wherein each unit cell includes a current source and at least two switching elements that are configured to couple the current source to one of a first output of the differential output or a second output of the differential output;
• an operational amplifier having an inverting input coupled to the first output and a non-inverting input coupled to the second output;
• and
• a transistor coupled to the second output and the output of the operational amplifier,
• wherein the operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

A processor, comprising:

• a digital phase-locked loop (PLL) unit that includes:
• a digital-to-analog converter (DAC) having a differential current output,
• an operational amplifier having an inverting input coupled to a first output of the differential current output and a non-inverting input coupled to a second output of the differential current output, and
• a transistor coupled to the second output and the output of the operational amplifier,
• wherein the operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

A processor, comprising:

• a circuit that includes:
• a digital-to-analog converter (DAC) having a differential output,
• an operational amplifier having an inverting input coupled to a first output of the differential output and a non-inverting input coupled to a second output of the differential output, wherein the first output is a non-inverting output of the DAC and the second output is an inverting output of the DAC, and
• a transistor coupled to the second output and the output of the operational amplifier,
• wherein the operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output, and the transistor is an NMOS (n-type Metal Oxide Semiconductor) transistor having a drain coupled to the second output, and a source coupled to a ground potential.

A processor, comprising:

• a circuit that includes:
• a digital-to-analog converter (DAC) having a differential output, wherein the DAC comprises a number of unit cells, and wherein each unit cell includes a current source and at least two switching elements that are configured to couple the current source to one of a first output of the differential output or a second output of the differential output;
• an operational amplifier having an inverting input coupled to the first output and a non-inverting input coupled to the second output, and
• a transistor coupled to the second output and the output of the operational amplifier,
• wherein the operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

A processor, comprising:

• a graphics processing unit that includes:
• a digital-to-analog converter (DAC) having a differential output,
• an operational amplifier having an inverting input coupled to a first output of the differential output and a non-inverting input coupled to a second output of the differential output, wherein the first output is a non-inverting output of the DAC and the second output is an inverting output of the DAC, and
• a transistor coupled to the second output and the output of the operational amplifier,
• wherein the operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

A processor, comprising:

• a system-on-chip (SoC) that includes:
• a digital-to-analog converter (DAC) having a differential output,
• an operational amplifier having an inverting input coupled to a first output of the differential output and a non-inverting input coupled to a second output of the differential output, wherein the first output is a non-inverting output of the DAC and the second output is an inverting output of the DAC, and
• a transistor coupled to the second output and the output of the operational amplifier,
• wherein the operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.