Input configuration for analog to digital converter
AssigneeHittite Microwave Corporation
InventorBjornar Hernes
Life of this patent
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Abstract
A circuit includes an input, two or more sampling capacitors each in a different channel, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means to use the voltage across the sampling capacitor for further processing in a hold phase. The two sampling capacitors operate in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in the hold phase.
Claims13
A circuit comprising:
- an input;
- at least two sampling capacitors arranged in at least two different channels, each sampling capacitor being coupled to the input when in a sampling phase for storing a value of an input signal,
- the sampling capacitors each having a reset phase to provide a given voltage to the sampling capacitor prior to the sampling phase, and each sampling capacitor having a hold phase following the sampling phase for further processing of the stored value of the input signal, and wherein the sampling capacitors operate in anti-phase to each other such that the reset phase and sampling phase of one channel are performed when the other channel is in a hold phase or idle.
A circuit comprising:
- an input;
- at least two sampling capacitors arranged in two different channels, the sampling capacitors coupled to the input in a sampling phase for storing a value of an input signal;
- the sampling capacitors also having a reset phase to provide a given voltage to the sampling capacitor prior to the sampling phase, and the sampling capacitors having a hold phase following the sampling phase for further processing of the stored value of the input signal;
- and
- an amplifier comprising one input stage per sampling capacitor and a common output stage, wherein the sampling capacitors anti-phase with respect to each other such that the reset phase and sampling phase of one channel are performed when the other channel is in a hold phase or idle.
A method of processing an input signal in a circuit comprising an input and two sampling capacitors, each arranged in a separate channel, the method comprising:
- (a) discharging each sampling capacitor to a given voltage in a reset phase;
- (b) connecting each sampling capacitor to the input and storing a value of the input signal at the sampling capacitor in a sampling phase following the reset phase;
- (c) processing the stored value of the input signal in a hold phase after the sampling phase;
- and
- (d) repeating steps (a) through (c) a plurality of times;
- wherein the sampling capacitors anti-phase with respect to each other such that the reset phase and sampling phase of one channel occur when the other channel is in a hold phase or idle.
Dependencies are inferred from the claim text.