Low-power voltage reference circuit

A method for providing a temperature-compensated reference voltage, comprising:

• controlling a current by sending a first control signal and a second control signal from a current mirror portion to a temperature-compensated output portion,
• wherein the current mirror portion includes at least two cascaded transistor pairs configured to generate the first control signal, and a feedback circuit coupled to the at least two cascaded transistor pairs,
• wherein the feedback circuit is configured to generate a second control signal,
• wherein the at least two cascaded transistor pairs include a first transistor pair of p-channel metal-oxide-semiconductor (PMOS) transistors and a second transistor pair of n-channel metal-oxide-semiconductor (NMOS) transistors,
• wherein the feedback circuit includes a third transistor pair,
• wherein a sleep mode circuit is coupled to the third transistor pair, wherein the sleep mode circuit includes a fourth transistor pair, wherein the sleep mode circuit is coupled to a power supply, wherein the sleep mode circuit is controlled by a sleep mode enable input, and wherein the sleep mode circuit is configured to provide a voltage from the power supply to the current mirror portion, and
• wherein the temperature-compensated output portion includes a very low threshold voltage (Vt) metal-oxide-semiconductor (MOS) transistor coupled in series with a negative temperature coefficient MOS transistor;
• passing the current through the very low Vt MOS transistor and the negative temperature coefficient MOS transistor,
• wherein the first control signal and the second control signal are configured to change a magnitude of the current;
• and
• generating the temperature-compensated reference voltage using the very low Vt MOS transistor and the negative temperature coefficient MOS transistor.

A temperature-compensated voltage reference circuit, comprising:

• means for controlling a current including:
• means for passing the current through at least two cascaded transistor pairs, wherein the at least two cascaded transistor pairs are configured to generate a first control signal, wherein the at least two cascaded transistor pairs include a first transistor pair of p-channel metal-oxide-semiconductor (PMOS) transistors and a second transistor pair of re-channel metal-oxide-semiconductor (NMOS) transistors;
• and
• means for passing the current through a feedback circuit, wherein the feedback circuit is coupled to the at least two cascaded transistor pairs, wherein the feedback circuit includes a third transistor pair, and wherein the feedback circuit is configured to generate a second control signal;
• means for passing the current through a very low threshold voltage (Vt) metal-oxide-semiconductor (MOS) transistor coupled in series with a negative temperature coefficient MOS transistor, wherein the first control signal and the second control signal are configured to change a magnitude of the current;
• and
• means for passing the current through a voltage adjust circuit, wherein the voltage adjust circuit has a voltage adjust input, the voltage adjust circuit configured to control a second magnitude of the current through the means for controlling the current by varying a variable resistance.

A non-transitory computer-readable medium, comprising instructions stored thereon that, if executed by a fabrication apparatus, cause the fabrication apparatus to fabricate at least a part of a device, comprising:

• a current mirror portion including:
• at least two cascaded transistor pairs configured to generate a first control signal, wherein the at least two cascaded transistor pairs include a first transistor pair of p-channel metal-oxide-semiconductor (PMOS) transistors and a second transistor pair of n-channel metal-oxide-semiconductor (NMOS) transistors;
• and
• a feedback circuit coupled to the at least two cascaded transistor pairs, wherein the feedback circuit includes a third transistor pair, and wherein the feedback circuit is configured to generate a second control signal;
• a sleep mode circuit that includes a fourth transistor pair, wherein the sleep mode circuit is coupled to a power supply, wherein the sleep mode circuit is coupled to the third transistor pair, wherein the sleep mode circuit is controlled by a sleep mode enable input, and wherein the sleep mode circuit is configured to provide a voltage from the power supply to the current mirror portion;
• and
• a temperature-compensated output portion coupled to the current mirror portion,
• wherein the temperature-compensated output portion comprises a very low threshold voltage (Vt) transistor coupled in series with a negative temperature coefficient transistor, and wherein the first control signal and the second control signal are configured to change a magnitude of a current passed through the temperature-compensated output portion.