US 8,786,349 B2Granted

Semiconductor device, electronic device having the same, and driving method of the same

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorHajime Kimura

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Abstract

A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

Claims22

Dependent claims

A semiconductor device comprising:

a first wiring;
a first switch comprising a first terminal and a second terminal;
the first terminal of the first switch being electrically connected to the first wiring;
a second switch comprising a first terminal and a second terminal, the first terminal of the second switch being electrically connected to the second terminal of the first switch;
a second wiring electrically connected to the second terminal of the second switch;
a capacitor comprising a first electrode and a second electrode, the first electrode being electrically connected to the second terminal of the first switch;
a third switch comprising a first terminal and a second terminal, the first terminal being electrically connected to the second electrode of the capacitor;
a third wiring electrically connected to the second terminal of the third switch;
a transistor comprising a gate, a first terminal, and a second terminal, the gate being electrically connected to the second electrode of the capacitor and to the first terminal of the third switch, and the first terminal being electrically connected to the third wiring;
and
a fourth wiring electrically connected to the second terminal of the transistor,
wherein an input signal is input to the second terminal of the second switch,
wherein the third wiring is configured to be set at a high power supply potential,
wherein the fourth wiring is configured to be set at a low power supply potential,
wherein the first wiring is configured to be set at a potential lower than the high power supply potential and higher than the low power supply potential, and
wherein the second electrode of the capacitor, the first terminal of the third switch, and the gate of the transistor are directly connected to a same electrical node.

13 more elements

A semiconductor device comprising:

a first wiring;
a first switch comprising a first terminal and a second terminal;
the first terminal of the first switch being electrically connected to the first wiring;
a second switch comprising a first terminal and a second terminal, the first terminal of the second switch being electrically connected to the second terminal of the first switch;
a second wiring electrically connected to the second terminal of the second switch;
a capacitor comprising a first electrode and a second electrode, the first electrode being electrically connected to the second terminal of the first switch;
a third switch comprising a first terminal and a second terminal, the first terminal being electrically connected to the second electrode of the capacitor;
a third wiring electrically connected to the second terminal of the third switch;
a transistor comprising a gate, a first terminal, and a second terminal, the gate being electrically connected to the second electrode of the capacitor and to the first terminal of the third switch, and the first terminal being electrically connected to the third wiring;
and
a fourth wiring electrically connected to the second terminal of the transistor,
wherein an input signal is input to the second terminal of the second switch, and
wherein the second electrode of the capacitor, the first terminal of the third switch, and the gate of the transistor are directly connected to a same electrical node.

10 more elements

A display device comprising:

a pixel portion;
a scanning driver circuit;
a signal driver circuit;
a first wiring;
a first switch comprising a first terminal and a second terminal;
the first terminal of the first switch being electrically connected to the first wiring;
a second switch comprising a first terminal and a second terminal, the first terminal of the second switch being electrically connected to the second terminal of the first switch;
a second wiring electrically connected to the second terminal of the second switch;
a capacitor comprising a first electrode and a second electrode, the first electrode being electrically connected to the second terminal of the first switch;
a third switch comprising a first terminal and a second terminal, the first terminal being electrically connected to the second electrode of the capacitor;
a third wiring electrically connected to the second terminal of the third switch;
a transistor comprising a gate, a first terminal, and a second terminal, the gate being electrically connected to the second electrode of the capacitor and to the first terminal of the third switch, and the first terminal being electrically connected to the third wiring;
and
a fourth wiring electrically connected to the second terminal of the transistor,
wherein an input signal is input to the second terminal of the second switch, and
wherein the second electrode of the capacitor, the first terminal of the third switch, and the gate of the transistor are directly connected to a same electrical node.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/559,662Filed 27 Jul 2012 · continuation
Priority: JP 2003-03305112 Feb 2003
Published: US 2012/0299885 A129 Nov 2012
Granted: 22 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H03K 19/01728
In field-effect transistor circuits: in synchronous circuits, i.e. by using clock signals
H03K 19/01855
Interface arrangements: synchronous, i.e. using clock signals
H03K
Pulse technique

Family

Application10/769,853Parent of this division · filed 3 Feb 2004
Application12/402,630Parent of this continuation · filed 12 Mar 2009
US 7,528,643 B2Parent of this division · filed 5 May 2009
US 2012/0299885 A1Pre-grant publication · published 29 Nov 2012
US 8,258,847 B2Parent of this continuation
Application12/402,630Parent of this division
US 2004/0155698 A1Published application
US 2009/0167404 A1Published application
US 8,786,349 B2This patent

From the US filing history. Foreign family members aren’t listed.

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