Delay circuits for simulating delays based on a single cycle of a clock signal

A delay circuit, comprising:

• a ring oscillator circuit comprising a delay chain comprising a plurality of delay elements, an inverted output of the delay chain coupled with an input of the delay chain, the ring oscillator circuit configured to generate one or more cycles of an oscillator clock signal in response to a clock cycle of a clock signal;
• a counter circuit communicatively coupled with the ring oscillator circuit, the counter circuit comprising
• a first counter configured to be triggered at a rising edge of the oscillator clock signal at an output of a delay element of the plurality of delay elements;
• a second counter configured to be triggered at a falling edge of the oscillator clock signal at the output of the delay element;
• a first buffer configured to store a number of clock cycles of the oscillator clock signal in response to the clock cycle of the clock signal based on count states of the first counter and the second counter;
• and
• a second buffer configured to store a bit pattern corresponding to a number of delay elements traversed in a partial clock cycle of the oscillator clock signal in response to the clock cycle of the clock signal, wherein the bit pattern is based on outputs of the plurality of delay elements,
• wherein the number of clock cycles stored in the first buffer and the bit pattern corresponding to the number of delay elements in the partial clock cycle correspond to a delay code for the clock signal, and wherein the delay code corresponds to a number of delay elements and wherein a sum of delays generated by the number of delay elements is substantially equal to a clock period of the clock signal.