Reset extender for divided clock domains

A system, comprising:

• a clock configured to generate a clock signal;
• a plurality of logic blocks, wherein each of the plurality of logic blocks includes a respective clock divider configured to divide the clock signal to produce a local clock signal, wherein each of the plurality of logic blocks includes a respective reset unit that is configured, in response to reset information, to enable the respective clock divider for that logic block while local circuitry for that logic block is being reset;
• and
• a power manager unit coupled to the plurality of logic blocks, wherein the power manager unit is configured to transmit the reset information to the plurality of logic blocks to cause the plurality of logic blocks to be reset.

A method, comprising:

• transmitting reset information to a plurality of logic blocks, each of which respectively includes a clock divider configured to receive a first clock signal and provide a divided clock signal in response;
• preventing the first clock signal from reaching the respective clock divider for each of the plurality of logic blocks;
• subsequent to said preventing, causing the respective clock divider for each of the plurality of logic blocks to be removed from reset;
• and
• subsequent to said causing the respective clock divider for each of the plurality of logic blocks to be removed from reset, causing the first clock signal to again be provided to the respective clock divider for each of the plurality of logic blocks.