Method for doubling the frequency of a reference clock
AssigneeQUALCOMM Incorporated
InventorEmmanouil Terrovitis
Life of this patent
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Abstract
A clock multiplier circuit includes a clock generator, a delay element, a logic gate, and a duty cycle correction circuit. The clock generator generates a clock signal. The delay element generates a delayed clock signal in response to the clock signal. The logic gate generates a frequency-multiplied clock signal in response to the clock signal and the delayed clock signal. The duty cycle correction circuit generates an adjustment signal based at least in part on the frequency-multiplied clock signal. The clock generator adjusts a duty cycle of the clock signal in response to the adjustment signal.
Claims26
A clock multiplier circuit, comprising:
- a clock generator to generate a clock signal, wherein the clock generator includes a control terminal;
- a delay element to generate a delayed clock signal in response to the clock signal;
- a logic gate to generate a frequency-multiplied clock signal in response to a combination of the clock signal and the delayed clock signal;
- and
- a duty cycle correction circuit, coupled between the logic gate and the control terminal of the clock generator, to generate an adjustment signal based at least in part on the frequency-multiplied clock signal, wherein the clock generator is to adjust a duty cycle of the clock signal in response to the adjustment signal.
A method for multiplying a frequency of a clock signal, the method comprising:
- generating the clock signal using a clock generator;
- generating a delayed clock signal in response to the clock signal;
- logically combining the clock signal and the delayed clock signal to generate a frequency-multiplied clock signal;
- generating an adjustment signal in response to the frequency-multiplied clock signal and providing the adjustment signal to the clock generator;
- and
- adjusting a duty cycle of the clock signal, using the clock generator, in response to the adjustment signal.
A clock multiplier circuit, comprising:
- means for generating a clock signal;
- means for generating a delayed clock signal in response to the clock signal;
- means for logically combining the clock signal and the delayed clock signal to generate a frequency-multiplied clock signal;
- and
- means for generating an adjustment signal in response to the frequency-multiplied clock signal and providing the adjustment signal to the means for generating the clock signal,
- wherein the means for generating the clock signal adjusts a duty cycle of the clock signal in response to the adjustment signal.
Dependencies are inferred from the claim text.