US 8,786,328 B2Granted

RF logic divider

AssigneeTexas Instruments Incorporated

InventorsSwaminathan Sankaran, Sudipto Chakraborty, Per T. Roine

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Abstract

An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch.

Claims12

Dependent claims

An apparatus comprising:

a plurality of latches coupled in series with one another in a ring configuration, wherein each latch includes:
a tri-state inverter with a first clock terminal and a second clock terminal;
a first resistor-capacitor (RC) network that is coupled to the first clock terminal;
and
a second RC network that is coupled to the second clock terminal;
and
a biasing network having:
a first bias voltage generator that is coupled to the first RC network for each latch;
and
a second bias voltage generator that is coupled to the second RC network for each latch,
wherein the first RC network further comprises:
a capacitor that is coupled to the first clock terminal and that is configured to receive a clock signal;
and
a resistor that is coupled to the first clock terminal and the first bias voltage generator,
wherein the capacitor, resistor, and clock signal further comprise a first capacitor, a first resistor, and a first clock signal, and wherein the second RC network further comprises:
a capacitor that is coupled to the first clock terminal and that is configured to receive a second clock signal;
and
a resistor that is coupled to the first clock terminal and the first bias voltage generator,
wherein each of the resistors allow inner transistors of a first latch of the plurality of latches and the second latch of the plurality of latches to be biased through coupled each of the resistors such that the gate voltages of these transistors are near or above their respective threshold voltages during operation.

16 more elements

An apparatus comprising:

a first latch having:
a first tri-state inverter with a first input terminal, a first output terminal, a first clock terminal, and a second clock terminal;
a first resistor-capacitor (RC) network that is coupled to the first clock terminal, wherein the first RC network is configured to receive a first clock signal;
and
a second RC network that is coupled to the second clock terminal, wherein the second RC network is configured to receive a second clock signal;
a second latch having:
a second tri-state inverter with a second input terminal, a second output terminal, a third clock terminal, and a fourth clock terminal, wherein the second output terminal is coupled to the first input terminal;
a third resistor-capacitor (RC) network that is coupled to the third clock terminal, wherein the third RC network is configured to receive the second clock signal;
and
a fourth RC network that is coupled to the fourth clock terminal, wherein the fourth RC network is configured to receive the first clock signal;
a biasing network having:
a first bias voltage generator that is coupled to the first and third RC networks;
and
a second bias voltage generator that is coupled to the second and fourth RC networks;
and
an inverter that is coupled to the first output terminal and the second input terminal,
wherein each of the first, second, third, and fourth RC networks further comprises:
a capacitor that is coupled to its clock terminal;
and
a resistor that is coupled to its clock terminal and its bias voltage generator;
wherein each of the first and second tri-state inverters further comprises:
a first PMOS transistor;
a second PMOS transistor that is coupled to the drain of the first PMOS transistor at its source;
a first NMOS transistor that is coupled to the drain of the second PMOS transistor at its drain;
and
a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and the gate of the first PMOS transistor at its gate,
wherein each of the resistors allow inner transistors of a first latch of the plurality of latches and the second latch of the plurality of latches to be biased through coupled each of the resistors such that the gate voltages of these transistors are near or above their respective threshold voltages during operation.

24 more elements

An apparatus comprising:

a phase/frequency detector (PFD) that is configured to receive a reference signal;
a charge pump that is coupled to the PFD;
a low pass filter (LPF) that is coupled to the charge pump;
a voltage controller oscillator (VCO) that is coupled to the LPF, wherein the VCO has a first VCO terminal and a second VCO terminal;
and
a divider having:
a first latch having:
a first tri-state inverter with a first input terminal, a first output terminal, a first clock terminal, and a second clock terminal;
a first resistor-capacitor (RC) network that is coupled to the first clock terminal, wherein the first RC network is coupled to the first VCO terminal;
and
a second RC network that is coupled to the second clock terminal, wherein the second RC network is coupled to the second VCO terminal;
a second latch having:
a second tri-state inverter with a second input terminal, a second output terminal, a third clock terminal, and a fourth clock terminal, wherein the second output terminal is coupled to the first input terminal and to the PFD;
a third resistor-capacitor (RC) network that is coupled to the third clock terminal, wherein the third RC network coupled to the second VCO terminal;
and
a fourth RC network that is coupled to the fourth clock terminal, wherein the fourth RC network is coupled to the first VCO terminal;
a biasing network having:
a first bias voltage generator that is coupled to the first and third RC networks;
and
a second bias voltage generator that is coupled to the second and fourth RC networks;
and
an inverter that is coupled to the first output terminal and the second input terminal,
wherein each of the first, second, third, and fourth RC networks further comprises:
a capacitor that is coupled to its clock terminal;
and
a resistor that is coupled to its clock terminal and its bias voltage generator,
wherein each of the first and second tri-state inverters further comprises:
a first PMOS transistor;
a second PMOS transistor that is coupled to the drain of the first PMOS transistor at its source;
a first NMOS transistor that is coupled to the drain of the second PMOS transistor at its drain;
and
a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and the gate of the first PMOS transistor at its gate,
wherein each of the resistors allow inner transistors of a first latch of the plurality of latches and the second latch of the plurality of latches to be biased through coupled each of the resistors such that the gate voltages of these transistors are near or above their respective threshold voltages during operation.

30 more elements

Dependencies are inferred from the claim text.