Partially programming an integrated circuit using control memory cells

A method of generating an implementation of a circuit design for an integrated circuit (IC), comprising:

• placing a first function of the circuit design on a first subset of programmable resources of the IC and a second function of the circuit design on a second subset of the programmable resources;
• wherein the first function is a partial configuration portion of the design, the second function is a partial reconfiguration portion of the design, and the second subset of programmable resources intersects the first subset of programmable resources;
• generating a first configuration bitstream having configuration data that configures each subset of configuration memory cells of the IC that are coupled to the first subset of programmable resources to implement the first function;
• generating a second configuration bitstream having configuration data that configures each subset of configuration memory cells coupled to the second subset of programmable resources to implement the second function;
• wherein at least one of the subsets of configuration memory cells that are coupled to the first subset of programmable resources and at least one of the subsets of configuration memory cells that are coupled to the second subset of programmable resources are included in one frame of a plurality of frames of the configuration memory cells of the IC;
• and
• generating a third configuration bitstream that programs to a first state, a partial reconfiguration control memory cell associated with the at least one of the subsets of configuration memory cells that are coupled to the first subset of programmable resources, wherein the first state enables programming of the at least one of the subsets of configuration memory cells.

A method of operating an integrated circuit (IC), comprising:

• inputting an initial bitstream that includes configuration data for one or more frames of configuration memory cells of the IC and configuration data that configures partial configuration control memory cells of the IC into a first state, wherein each frame of the one or more frames includes a plurality of subsets of configuration memory cells, and each subset of configuration memory cells of the frame is coupled to one of the programmable resources, and each subset of configuration memory cells is coupled to a respective partial configuration control memory cell;
• programming the one or more frames of configuration memory cells with the initial bitstream;
• operating the IC as configured with the initial bitstream;
• in response to a reconfiguration trigger signal, configuring to a second state the respective partial configuration control memory cell coupled to one subset of the plurality of subsets of configuration memory cells of one frame of the one or more frames of configuration memory cells;
• inputting a first partial bitstream that includes configuration data for at least the one frame of the one or more frames of configuration memory cells, wherein the first partial bitstream includes a quantity of configuration data for the plurality of subsets of configuration cells of the one frame;
• enabling programming of the one subset of configuration memory cells with configuration data from the first partial bitstream in response to the respective partial configuration control memory cell being in the second state;
• disabling programming of each other subset of the one frame other than the one subset of configuration memory cells of the one frame in response to the respective partial configuration control memory cell coupled to the other subset of configuration memory cells of the one frame being in the first state;
• and
• programming the one subset of configuration memory cells with configuration data from the first partial bitstream.