Multi-path power switch scheme for functional block wakeup

A method comprising:

• sequentially activating a first plurality of power switches coupled between a global voltage node and a local voltage node of a power gated circuit block in an integrated circuit;
• activating a first timer concurrent with beginning activation of the first plurality of power switches;
• the first timer indicating when a first predetermined amount of time has elapsed;
• and
• sequentially activating a second plurality of power switches coupled between the global voltage node and the local voltage node responsive to the timer indicating that the first predetermined time has elapsed, the first predetermined time comprising a plurality of clock cycles.

An integrated circuit comprising:

• a plurality of power gated functional units including a first functional unit and a second functional unit;
• a power control unit control unit coupled to the first and second functional units, wherein the power control unit is configured to, responsive to a first request to power up the first functional unit and a subsequent second request to power up the second functional unit:
• initiate activation of a first plurality of power switches associated with the first functional block;
• inhibit, for a first predetermined time, activation of a second plurality of power switches associated with the second functional block;
• and
• initiate activation of the second plurality of power switches responsive to the first predetermined time elapsing, the first predetermined time comprising a plurality of clock cycles.

An integrated circuit comprising:

• a first power gated functional unit including a first plurality of transistors coupled between a global voltage node and a first local voltage node, and a second plurality of transistors coupled between the global and first local voltage nodes, wherein the transistors of the first plurality are configured to be sequentially activated responsive to the first functional unit receiving a first enable signal, and wherein the first functional unit further includes a first timer configured to initiate sequential activation of the transistors of the second plurality responsive to determining a first time period has elapsed, the first time period comprising a first plurality of clock cycles;
• a second power gated functional unit including a third plurality of transistors coupled between the global voltage node and a second local voltage node, and a fourth plurality of transistors coupled between the global and second local voltage nodes, wherein the transistors of the third plurality are configured to be sequentially activated responsive to the second power gated functional unit receiving a second enable signal, and wherein the second power gated functional unit further includes a second timer configured to initiate sequential activation of the transistors of the fourth plurality responsive to determining a second time period has elapsed, the second time period comprising a second plurality of clock cycles;
• a power control unit coupled to provide the first enable signal to the first functional unit and the second enable signal to the second functional unit responsive to first and second power on requests, respectively, and wherein the power control unit is configured to, responsive to asserting the first enable signal, inhibit assertion of the second enable signal for a third time period.