Effective current sensing for high voltage switching regulators

An integrated circuit device having input current and output voltage sensing for control of a voltage switching regulator, said integrated circuit device comprising:

• a power switching transistor having a drain coupled to a voltage source, a source coupled to an inductor of the voltage switching regulator, and a gate for controlling the power switching transistor, wherein the gate receives a pulse width modulation (PWM) control signal;
• first and second transistors connected in series, wherein the series connected first and second transistors are connected in parallel with the source and drain of the power switching transistor, and a first input of a current control circuit is coupled to a drain of the first transistor and a source of the second transistor;
• and
• a sensing transistor having a drain and a gate connected to a drain and a gate, respectively, of the second transistor, and a source connected to a second input of the current control circuit;
• and
• a switch which is controlled to feed the pulse width modulation (PWM) control signal to the gate of the sensing transistor and to a gate of the second transistor when the power switching transistor is on and a standby voltage value when the power switching transistor is off, wherein a voltage at the gates of the second and sensing transistors does not exceed one-half (½) of the sourced voltage.

A method for reducing current sensing delay when measuring current to a voltage switching regulator and generating corresponding sense current values for control of the voltage switching regulator, said method comprising the steps of:

• providing first and second transistors coupled in series, wherein the first and second transistors are coupled in parallel with a power switching transistor which is coupled with a power source, and a sensing transistor coupled with said power source;
• regulating a sensing current by a regulating circuit coupled with a node between said first and second transistors and said sensing transistor;
• wherein the first transistor is controlled by a control signal provided for the power switching transistor;
• wherein the sensing transistor and the second transistor are controlled in a first mode to receive the control signal for said power switching transistor and in a second mode to be biased to be switched on wherein the first mode is a power switching transistor on mode and the second mode is a power switching transistor off mode.