US 8,786,091 B2Granted

Semiconductor apparatus having a high-aspect penetrating electrode and manufacturing method thereof

AssigneeCanon Kabushiki Kaisha

InventorTadayoshi Muta

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Abstract

A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. In one embodiment a first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.

Claims11

Dependent claims

A semiconductor apparatus, comprising:

a semiconductor substrate having a front surface and a rear surface;
a first electrode provided on said front surface;
a second electrode provided on said rear surface;
a contact hole formed in said semiconductor substrate, penetrating said semiconductor substrate so as to connect said first electrode and said second electrode;
an insulating film formed on a side of said contact hole;
and
a conductive member filled in said contact hole so as to connect to said first electrode,
wherein said second electrode has an extended portion that extends from said rear surface, said extended portion being formed on a portion of said insulating film formed on the side of said contact hole, and said extended portion and said conductive member, which is filled in said contact hole so as to overlap with said extended portion, are connected, to connect electrically said first electrode and said second electrode.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/059,720Filed 19 Oct 2009
Priority: JP 2008-27101021 Oct 2008
Published: US 2011/0147941 A123 Jun 2011
Granted: 22 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0234
The interconnections being through-semiconductor vias: comprising etching via holes that stop on pads or on electrodes
H10W 20/0242
The interconnections being through-semiconductor vias: comprising etching via holes from the back sides of the chips, wafers or substrates
H10W 20/0261
The interconnections being through-semiconductor vias: characterised by the filling method or the material of the conductive fill

Family

US 2011/0147941 A1Pre-grant publication · published 23 Jun 2011
US 8,786,091 B2This patent

From the US filing history. Foreign family members aren’t listed.

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