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US 8,786,088 B2Granted
Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction
AssigneeGlobalfoundries Inc.
InventorsTorsten Huisinga, Jens Heinrich, Kai Frohberg, Frank Feustel
Life of this patent
Estimating the term…
Abstract
In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses.
Claims12
A semiconductor device, comprising:
- a metallization system comprising a metal line layer formed above a substrate, said metal line layer comprising a metal line laterally embedded in a porous dielectric material, said metallization system further comprising a via layer comprising a via connecting to said metal line, said via being laterally embedded in a non-porous dielectric material along a height of said via, wherein said non-porous dielectric material comprises an etch stop layer and at least one further material formed at least locally at said via above said etch stop layer and wherein said at least one further material forms material portions, each of which is laterally embedded in a further porous dielectric material;
- and
- a bump structure configured to be connected to a complementary contact structure of a package substrate by using a lead-free solder material.
A semiconductor device, comprising:
- a plurality of stacked metal line layers formed above a substrate, each metal line layer comprising a plurality of metal lines formed in an ultra low-k dielectric material;
- at least one intermediate via layer located between two of said plurality of stacked metal line layers, said at least one intermediate via layer comprising a metal-containing via formed in a dielectric material, at least a portion of which has a greater dielectric constant than said ultra low-k dielectric material, said at least a portion extending along a total height of said via, wherein said dielectric material of greater dielectric constant forms a plurality of material portions, each of which is laterally enclosed by an ultra low-k dielectric material;
- and
- a bump structure comprising contact elements for forming an intermetallic connection with complementary contact elements of a package substrate on the basis of a lead-free contact regime wherein said plurality of material are positioned on an etch stop layer.
1 more element
Dependencies are inferred from the claim text.