Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance

A heterojunction bipolar transistor comprising:

• a trench isolation region in a semiconductor substrate;
• a collector region in said substrate positioned laterally adjacent to said trench isolation region;
• a seed layer comprising:
• a first monocrystalline center section covering said collector region and further extending laterally onto said trench isolation region;
• and
• a first polycrystalline outer section positioned laterally adjacent to said first monocrystalline center section;
• and
• an intrinsic base layer adjacent to said seed layer, said intrinsic base layer comprising any one of a silicon germanium intrinsic base layer, a silicon germanium intrinsic base layer doped with carbon and a silicon germanium carbide intrinsic base layer,
• said first polycrystalline outer section and an edge portion of said first monocrystalline center section above said trench isolation region being doped with inert ions.

A transistor comprising:

• a trench isolation region in a semiconductor substrate;
• a collector region in said substrate positioned laterally adjacent to said trench isolation region;
• a seed layer comprising:
• a first monocrystalline center section covering said collector region and further extending laterally onto said trench isolation region;
• and
• a first polycrystalline outer section positioned laterally adjacent to said first monocrystalline center section;
• an intrinsic base layer adjacent to said seed layer, said intrinsic base layer comprising:
• a second monocrystalline center section aligned above and approximately equal in size to said first monocrystalline center section such that said second monocrystalline center section is wider than said collector region;
• and
• a second polycrystalline outer section on said first polycrystalline outer section and positioned laterally adjacent to said second monocrystalline center section;
• an extrinsic base layer above said intrinsic base layer;
• and
• an emitter layer extending vertically through said extrinsic base layer to an inner portion of said second monocrystalline center section of said intrinsic base layer above said collector region,
• said emitter layer being electrically isolated from said extrinsic base layer, and
• said extrinsic base layer having a monocrystalline link-up region in contact with an edge portion of said second monocrystalline center section of said intrinsic base layer and offset vertically from said collector region in said substrate below.

A heterojunction bipolar transistor comprising:

• a trench isolation region in a semiconductor substrate;
• a collector region in said substrate positioned laterally adjacent to said trench isolation region;
• a seed layer comprising:
• a first monocrystalline center section covering said collector region and further extending laterally onto said trench isolation region;
• and
• a first polycrystalline outer section positioned laterally adjacent to said first monocrystalline center section;
• an intrinsic base layer adjacent to said seed layer, said intrinsic base layer comprising any one of a silicon germanium intrinsic base layer, a silicon germanium intrinsic base layer doped with carbon and a silicon germanium carbide intrinsic base layer and said intrinsic base layer further comprising:
• a second monocrystalline center section aligned above and approximately equal in size to said first monocrystalline center section such that said second monocrystalline center section is wider than said collector region;
• and
• a second polycrystalline outer section on said first polycrystalline outer section and positioned laterally adjacent to said second monocrystalline center section;
• an extrinsic base layer above said intrinsic base layer;
• and
• an emitter layer extending vertically through said extrinsic base layer to an inner portion of said second monocrystalline center section of said intrinsic base layer above said collector region,
• said emitter layer being electrically isolated from said extrinsic base layer, and
• said extrinsic base layer having a monocrystalline link-up region in contact with an edge portion of said second monocrystalline center section of said intrinsic base layer and offset vertically from said collector region in said substrate below.