Optimized channel implant for a semiconductor device and method of forming the same

A system for transmitting or receiving data, the system comprising:

• a memory device for storing a program;
• and
• a processor in communication with the memory device,
• wherein the memory device comprises:
• a silicon trace doped with a first dopant;
• an isolation region formed in the silicon trace;
• a first polysilicon trace formed on the silicon trace;
• a second polysilicon trace adjacent to the first polysilicon trace and formed on the silicon trace and the isolation region;
• a source/drain region formed in the silicon trace between the first and the second polysilicon traces, wherein the source/drain region is doped with a second dopant opposite the first dopant;
• a channel region in the silicon trace under the first polysilicon trace and doped with the first dopant;
• a doping region formed in the silicon trace and between the source/drain region and the isolation region, wherein the doping region is doped with the second dopant and is partially overlapped by the second polysilicon trace;
• and
• a dielectric layer formed on the first and second polysilicon traces and on the source/drain region,
• wherein the dielectric layer includes a cavity filled with a conductive material to form a contact area, the contact area overlapping part of the source/drain region and the second polysilicon trace to electrically connect the second polysilicon trace with the source/drain region.

A semiconductor memory card, comprising:

• an interface part that interfaces with an external device;
• a controller that communicates with the interface part and a memory device via address and data buses, wherein the memory device comprises:
• a silicon trace doped with a first dopant;
• an isolation region formed in the silicon trace;
• a first polysilicon trace formed on the silicon trace;
• a second polysilicon trace adjacent to the first polysilicon trace and formed on the silicon trace and the isolation region;
• a source/drain region formed in the silicon trace between the first and the second polysilicon traces wherein the source/drain region is doped with a second dopant opposite the first dopant;
• a channel region in the silicon trace under the first polysilicon trace and doped with the first dopant;
• a doping region formed in the silicon trace and between the source/drain region and the isolation region, wherein the doping region is doped with the second dopant and is partially overlapped by the second polysilicon trace;
• and
• a dielectric layer formed on the first and second polysilicon traces and on the source/drain region, wherein the dielectric layer includes a cavity filled with a conductive material to form a contact area, the contact area overlapping part of the source/drain region and the second polysilicon trace to electrically connect the second polysilicon trace with the source/drain region.