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US 8,786,025 B2Granted
Semiconductor device and method for forming same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJui-Yao Lai, Chun-Yi Lee, Shyh-Wei Wang, Yen-Ming Chen
Life of this patent
Estimating the term…
Abstract
A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.
Claims20
A semiconductor device comprising:
- a first dielectric layer over a semiconductor substrate;
- an opening within the first dielectric layer;
- a second dielectric layer lining the opening;
- a barrier metal layer overlying the second dielectric layer within the opening;
- a gate metal layer overlying the barrier metal layer within the opening;
- a third dielectric layer over the gate metal layer, wherein the barrier metal layer and the gate metal layer form a first resistor;
- a PMOS device on the semiconductor substrate, wherein the PMOS device comprises a gate electrode, the gate electrode comprising a first material, the barrier metal layer comprising the first material;
- and
- an NMOS device on the semiconductor substrate, wherein the NMOS device is free from the first material, wherein the PMOS device, the NMOS device, and the third dielectric layer each have a top surface that is planar to each other.
6 more elements
A semiconductor device comprising:
- a PMOS device on a substrate, wherein the PMOS device comprises a gate electrode, the gate electrode comprising a first material;
- an NMOS device on the substrate, wherein the NMOS device does not contain the first material;
- and
- a resistor on the substrate, the resistor having a top surface that is coplanar with a top surface of the PMOS device and a top surface of the NMOS device, wherein the resistor further comprises:
- an opening within a first dielectric layer;
- a continuous second dielectric layer around the sides of the opening;
- a barrier metal lining the continuous second dielectric layer, wherein the barrier metal comprises the first material;
- a gate metal over the barrier metal;
- and
- a third dielectric layer over the gate metal.
7 more elements
A semiconductor device comprising:
- a first dielectric layer over a semiconductor substrate;
- an NMOS gate electrode extending through the first dielectric layer;
- a PMOS gate electrode extending through the first dielectric layer, wherein the PMOS gate electrode comprises at least one material that is not within the NMOS gate electrode;
- and
- a resistor, wherein the resistor has a first top surface that is planar with a second top surface of the NMOS gate electrode and a third top surface of the PMOS gate electrode, the resistor further comprising:
- an opening extending through the first dielectric layer;
- a second dielectric layer covering a bottom and sidewalls of the opening;
- a barrier metal layer over the second dielectric layer, wherein the barrier metal layer comprises the at least one material;
- a gate metal layer over the barrier metal layer within the opening;
- and
- a third dielectric layer over the gate metal layer.
8 more elements
Dependencies are inferred from the claim text.