Back to results
US 8,786,023 B2Granted
Embedded non-volatile memory
AssigneeContour Semiconductor, Inc.
InventorsDaniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeContour Semiconductor, Inc.
InventorsDaniel R. Shepard, Mac D. Apodaca, Thomas Michael Trent, James Juen Hsu
Estimating the term…
The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.
A CMOS logic device comprising MOS transistor logic and one or more diode memory arrays whereby the material to form the diodes of the memory array is deposited or grown after the MOS transistor gate material is deposited and before the annealing of any silicide in the MOS transistor contacts, and further comprising cups that are filled with a material that performs the function of an information storage element.
An electronic system comprising a memory device whereby the memory device comprises MOS transistor logic and one or more diode memory arrays whereby the material to form the diodes of the memory array is deposited or grown after the MOS transistor gate material is deposited and before the annealing of any silicide in the MOS transistor contacts, and whereby the diodes of the memory array are comprised by information storage cells that also comprise cups that are filled with a material that performs the function of an information storage element.
An electronic system comprising a memory device whereby the memory device comprises MOS transistor logic and one or more diode memory arrays whereby the material to form the diodes of the memory array is deposited or grown after the MOS transistor gate material is deposited and before the annealing of any silicide in the MOS transistor contacts, and further comprising (i) contacts between the silicon on the substrate and one or more metal layers formed above the substrate and (ii) cups formed by the selective removal of said contacts.
Dependencies are inferred from the claim text.