US 8,786,019 B2Granted

CMOS FinFET device

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsCheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann

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Abstract

A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.

Claims20

Dependent claims

A CMOS FinFET device comprising:

a substrate including a first region and a second region;
a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region;
an insulation material disposed on the substrate and between the first and second fins;
a first portion of the first fin comprising a material that is the same material as the substrate;
a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin;
a first portion of the second fin comprising a material that is the same material as the substrate;
a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin;
and
a gate structure disposed on a central portion of the first fin including the III-V semiconductor material separating source and drain regions of a N-type metal-oxide-semiconductor (NMOS) fin-like field effect transistor (FinFET) device of the CMOS FinFET device and disposed on a central portion of the second fin including the Ge material separating source and drain regions of a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device of the CMOS FinFET device,
wherein the source and drain regions of the NMOS device define a channel region of the NMOS device therebetween, and
wherein the source and drain regions of the PMOS device define a channel region of the PMOS device therebetween.

8 more elements

A CMOS FinFET device comprising:

a substrate including first and second regions;
a fin structure including first and second fins formed over the substrate, the first fin being formed in the first region and the second fin being formed in the second region;
an insulation material formed over the substrate such that the first fin is interposed between the insulation material in the first region and the second fin is interposed between the insulation material in the second region;
a III-V semiconductor material formed over the first fin and interposed between the insulation material in the first region;
a germanium (Ge) material formed over the second fin and interposed between the insulation material in the second region;
and
a gate structure disposed on the III-V semiconductor material separating source and drain regions of a N-type metal-oxide-semiconductor (NMOS) fin-like field effect transistor (FinFET) device of the CMOS FinFET device and disposed on the Ge material separating source and drain regions of a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device of the CMOS FinFET device.

4 more elements

A CMOS FinFET device comprising:

a substrate including a N-type metal-oxide-semiconductor (NMOS) device and a P-type metal-oxide-semiconductor (PMOS) device;
a fin of the NMOS device interposed between first and second portions of an insulation material, wherein the fin of the NMOS device includes a lower portion, a middle portion, and an upper portion, wherein the lower portion is formed within the substrate, the middle portion is formed by depositing a III-V semiconductor material over the lower portion, and the upper portion is formed by depositing a first doped material over the III-V semiconductor material;
a fin of the PMOS device interposed between the second portion and a third portion of the insulation material, wherein the fin of the PMOS device includes a lower portion, a middle portion, and an upper portion, wherein the lower portion is formed within the substrate, the middle portion is formed by depositing a germanium (Ge) material over the lower portion, and the upper portion is formed depositing a second doped material over the Ge material;
and
a gate structure disposed over a channel region and separating source and drain regions of the NMOS device and disposed over a channel region and separating source and drain regions of the PMOS device, wherein the gate structure extends from the NMOS device over the second portion of the insulation material to the PMOS device.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/874,627Filed 1 May 2013 · division
Priority: 30 Dec 2011
Published: US 2013/0168771 A13 Oct 2013
Granted: 22 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 86/215
The substrates comprising an insulating layer on a semiconductor body, e.g. SOI: comprising FinFETs
H10D 30/751
Insulated-gate field-effect transistors [IGFET]: having composition variations in the channel regions
H10D 62/82
Characterised by the materials: heterojunctions
H10D 84/0193
The components including complementary IGFETs, e.g. CMOS devices: the components including FinFETs

Family

Application13/340,937Parent of this division · filed 30 Dec 2011
US 2013/0256799 A1Pre-grant publication · published 3 Oct 2013
US 8,486,770 B1Parent of this division
US 2013/0168771 A1Published application
US 8,786,019 B2This patent

From the US filing history. Foreign family members aren’t listed.

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