US 8,786,014 B2Granted

Vertical channel transistor array and manufacturing method thereof

AssigneePowerchip Technology Corporation

InventorYukihiro Nagai

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Abstract

A vertical channel transistor array includes a plurality of embedded bit lines, a plurality of bit line contacts, a plurality of embedded word lines, and a current leakage isolation structure. An active area of a vertical channel transistor is defined by the semiconductor pillars. The embedded bit lines are disposed in parallel in a semiconductor substrate and extended in a column direction. Each of the bit line contacts is respectively disposed at a side of one of the embedded bit lines. The embedded word lines are disposed in parallel above the embedded bit lines and extended in a row direction. Besides, the embedded word lines and the semiconductor pillars in the same row are connected but spaced by a gate dielectric layer. The current leakage isolation structure is disposed at ends of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.

Claims9

Dependent claims

A vertical channel transistor array, comprising:

a plurality of semiconductor pillars disposed in a semiconductor substrate and arranged in a column and row array, an active area of a vertical channel transistor being defined by the semiconductor pillars;
a plurality of embedded bit lines disposed in parallel in the semiconductor substrate and extended in a column direction, the embedded bit lines being electrically connected to the semiconductor pillars in the same column;
and
a plurality of embedded word lines disposed in parallel above the embedded bit lines and extended in a row direction, the embedded word lines and the semiconductor pillars in the same row being connected and spaced by a gate dielectric layer,
wherein each of the embedded word lines is connected to first sides of the semiconductor pillars in the same row, not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides;
and only one embedded word lines is correspondingly connected to the semiconductor pillars arranged in one row.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/008,024Filed 18 Jan 2011
Published: US 2012/0181606 A119 Jul 2012
Granted: 22 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 12/01
Dynamic random access memory [DRAM] devices: manufacture or treatment
H10B 12/053
Making the transistor: the transistor being at least partially in a trench in the substrate
H10B 12/34
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the transistor being at least partially in a trench in the substrate
H10B 12/482
Data lines or contacts therefor: bit lines

Family

US 2012/0181606 A1Pre-grant publication · published 19 Jul 2012
US 8,786,014 B2This patent

From the US filing history. Foreign family members aren’t listed.

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