N-channel metal-oxide field effect transistor with embedded high voltage junction gate field-effect transistor

A method for manufacturing a semiconductor device comprising:

• providing a P-type substrate;
• providing an N-type well region disposed adjacent to the substrate;
• providing a P-type well region disposed adjacent to the N-type well region;
• and
• providing first and second N+ doped regions disposed adjacent to the N-type well region and on opposing sides of the P-type well region;
• wherein the P-type well region comprises a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.

A semiconductor device comprising:

• a P-type substrate;
• an N-type well region disposed adjacent to the substrate;
• a first P-type well region disposed adjacent to the N-type well region,
• a second P-type well region disposed adjacent to the N-type well region and the substrate, the N-type well region encompassing the first P-type well region such that at least a portion of the N-type well region is interposed between the first and second P-type well regions;
• and
• first and second N+ doped regions disposed adjacent to the N-type well region and on opposing sides of the first P-type well region;
• wherein the second P-type well region comprises a second P+ doped region and the first P-type well region comprises a first P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure;
• and
• further wherein at least a portion of the second P-type well region is interposed between the first P+ doped region and the first N+ doped region.