Non-planar semiconductor device having channel region with low band-gap cladding layer

A semiconductor device, comprising:

• a hetero-structure disposed above a substrate and comprising a three-dimensional semiconductor body with a channel region comprising an inner region having a first band gap and an outer cladding layer at least partially surrounding the inner region, the cladding layer having a second, narrower band gap;
• a gate stack disposed on and at least partially surrounding the channel region, the gate stack comprising a gate dielectric layer disposed on the cladding layer and a gate electrode disposed on the gate dielectric layer, wherein the cladding layer only partially surrounds the inner region of the channel region, and the gate stack only partially surrounds the channel region;
• and
• source and drain regions disposed in the three-dimensional semiconductor body, on either side of channel region.

A semiconductor structure, comprising:

• a first semiconductor device, comprising:
• a first vertical arrangement of a plurality of nanowires disposed above a substrate, each nanowire comprising an inner region having a first band gap and an outer cladding layer surrounding the inner region, the cladding layer having a second, narrower band gap;
• a first gate stack disposed on and completely surrounding a channel region of each of the nanowires, the first gate stack comprising a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer;
• and
• source and drain regions disposed on either side of the channel regions of the nanowires of the first vertical arrangement of the plurality of nanowires;
• and
• a second semiconductor device, comprising:
• a second vertical arrangement of a plurality of nanowires disposed above the substrate;
• a second gate stack disposed on and completely surrounding a channel region of each of the nanowires, the second gate stack comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer;
• and
• source and drain regions disposed on either side of the channel regions of the nanowires of the second vertical arrangement of the plurality of nanowires.

A semiconductor device, comprising:

• a hetero-structure disposed above a substrate and comprising a three-dimensional semiconductor body with a channel region comprising an inner region having a first band gap and an outer cladding layer at least partially surrounding the inner region, the cladding layer having a second, narrower band gap, the three-dimensional semiconductor body horizontally oriented with respect to the substrate;
• a gate stack disposed on and at least partially surrounding the channel region, the gate stack comprising a gate dielectric layer disposed on the cladding layer and a gate electrode disposed on the gate dielectric layer, wherein the cladding layer completely surrounds the inner region of the channel region, and the gate stack completely surrounds the channel region;
• and
• source and drain regions disposed in the three-dimensional semiconductor body, on either side of channel region.