Etch bias homogenization

A method of forming a memory device, comprising:

• forming an active memory array in an active array area using a plurality of conductive material levels;
• forming a number of conductive line socket regions adjacent edges of the array area;
• forming a number of first inactive arrays in corner regions adjacent a number of conductive line socket regions;
• and
• forming a number of second inactive arrays outside of the array area, the number of conductive line socket regions, and the corner regions
• wherein forming an active memory array in an array area using a plurality of conductive material levels includes:
• forming conductive material at respective levels over a substrate;
• electrically coupling a first portion of the conductive material in the active array area to corresponding circuitry on the substrate via a second portion of the conductive material inside the second inactive array area during patterning of a particular one of the respective levels of conductive material so that each respective level of conductive material has a homogenized etch bias as that of another particular one of the respective levels of conductive material during patterning thereof;
• and
• patterning each respective level of conductive material electrically coupled to corresponding circuitry on the substrate.

A method of forming a memory device, comprising:

• forming over a substrate a plurality of metal levels metal levels coupled to CMOS devices associated with an active memory array in each of an active array area, an inactive array area, a first socket region, a second socket region, a third socket region, a decoder area, a first peripheral area, and a second peripheral area;
• electrically coupling the plurality of metal levels metal levels so as to have a homogenized etch bias during patterning thereof by:
• interconnecting a lowest metal level of the plurality of metal levels to the substrate during patterning of the lowest metal level;
• interconnecting each higher metal level of the plurality of metal levels to a respective lower metal level of the plurality of metal levels during patterning of each higher metal level;
• forming a glue metal level over a highest metal level of the plurality of metal levels;
• interconnecting the glue metal level in the inactive array area to the highest metal level before patterning the glue metal level;
• forming the active memory array in the array area over the glue metal level;
• and
• forming a metal level over the glue level in each of an array area, a first socket region, a second socket region, a third socket region, a decoder area, a first peripheral area, and a second peripheral area.

A method of forming a memory device, comprising:

• forming conductive material at respective levels over a substrate;
• electrically coupling each respective level of conductive material to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof;
• and
• patterning each respective level of conductive material electrically coupled to corresponding circuitry on the substrate,
• wherein electrically coupling conductive material from which conductive lines of an active memory array will be patterned through conductive material at a glue level G1 includes forming a grid of conductive lines in an area outside the socket region and an area of the active memory array from the conductive material at a glue level G1, the grid of conductive lines being formed around each of a number of inactive arrays.