Post-gate shallow trench isolation structure formation
AssigneeInternational Business Machines Corporation
InventorsXiaojun Yu, Brian J. Greene, Yue Liang
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AssigneeInternational Business Machines Corporation
InventorsXiaojun Yu, Brian J. Greene, Yue Liang
Estimating the term…
Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.
A method of forming a semiconductor structure comprising:
A method of forming a semiconductor structure comprising:
A method of forming a semiconductor structure comprising:
Dependencies are inferred from the claim text.