CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

A method for fabricating a semiconductor structure comprising:

• forming a first gate stack upon a first region of a semiconductor substrate, said first gate stack comprising a first gate dielectric and a first metal gate material layer;
• forming a material stack of a dielectric material layer and a second metal gate material layer, said dielectric material layer including a second gate dielectric and an etch stop layer that comprise a same material or a related material that is deposited or thermally grown, wherein said second gate dielectric is formed upon a second region of said semiconductor substrate that is laterally adjacent to said first region, and said etch stop layer is formed on sidewalls and a top surface of said first gate stack;
• forming a block mask over said second gate dielectric;
• removing portions of said second metal gate material layer and said etch stop layer from above a top surface of said first metal gate material layer while said block mask protects another portion of said second metal gate material layer overlying said second gate dielectric, wherein topmost surfaces of remaining portions of said second metal gate material layer and said second gate dielectric are formed above a first horizontal plane including a bottom surface of said first gate stack and below a second horizontal plane including a top surface of said first gate stack, and a remaining portion of said second gate dielectric is in physical contact with said first gate stack;
• forming a silicon gate material layer upon said first gate stack and upon said second gate dielectric after said removal of said portions of said second metal gate material layer and said etch stop layer;
• forming a planarizing layer upon said silicon gate material layer;
• and
• etching non-selectively, while a vertical portion of said material stack that includes a vertical portion of said second metal gate material layer is present on a sidewall surface of a remaining portion said first metal gate material layer, said planarizing layer and said silicon gate material layer to form a second gate stack laterally adjacent said first gate stack while using said etch stop layer as an etch indicator layer.

A method for fabricating a semiconductor structure comprising:

• forming a first gate stack upon a first region of a semiconductor substrate, said first gate stack comprising a first gate material layer;
• forming a material stack of a dielectric material layer and a metal gate material layer, said dielectric material layer including an etch stop layer and a second gate dielectric, wherein said etch stop layer is formed on a top surface and a sidewall surface of said first gate material layer, and said second gate dielectric is formed upon said first gate stack and a laterally adjacent second region of said semiconductor substrate;
• forming a block mask over said second gate dielectric;
• removing portions of said metal gate material layer and said etch stop layer from above a top surface of said first gate material layer while said block mask protects another portion of said metal gate layer overlying said second gate dielectric, wherein topmost surfaces of remaining portions of said metal gate material layer and said second gate dielectric are formed above a first horizontal plane including a bottom surface of said first gate stack and below a second horizontal plane including a top surface of said first gate stack, and a remaining portion of said second gate dielectric is in physical contact with said first gate stack;
• forming a second gate material layer upon said first gate stack and upon said second gate dielectric after said removal of said portions of said metal gate layer and said etch stop layer;
• forming a planarizing layer upon said second gate material layer;
• and
• simultaneously etching non-selectively, while a vertical portion of said material stack that includes a vertical portion of said metal gate material layer is present on a sidewall surface of a remaining portion of said first gate material layer, said planarizing layer and said second gate material layer while said etch stop layer is present on said top surface and said sidewall surface of said first gate material layer, to form a second gate stack laterally adjacent said first gate stack, wherein said etch stop layer serves as an etchback indicator layer during said simultaneous etching.