Back to results
US 8,785,261 B2Granted
Microelectronic transistor having an epitaxial graphene channel layer
AssigneeIntel Corporation
InventorSean King
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to forming a graphene layer as a channel layer for a microelectronic transistor.
Claims25
A method of fabricating a transistor comprising:
- providing a structural substrate comprising silicon;
- forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer;
- forming a graphene layer on the formation substrate comprising annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane to reduce and desorb surface oxides at temperatures of about 700-900° C. and forming the graphene layer by silicon volatization at temperature of about 950° C.;
- forming a source region abutting the graphene layer;
- forming a drain region abutting the graphene layer;
- forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
- and
- forming a gate abutting the gate dielectric.
5 more elements
A method of forming a transistor comprising:
- depositing a thermodynamically unstable XC carbide layer on a formation substrate comprising depositing amorphous germanium carbide on a (0001)6H-SiC substrate;
- decomposing the XC carbide layer into an X component and carbon;
- volatilizing the X component;
- forming a graphene layer from the carbon;
- forming a source region abutting the graphene layer;
- forming a drain region abutting the graphene layer;
- forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
- and
- forming a gate abutting the gate dielectric.
6 more elements
A method of forming a transistor comprising:
- depositing a thermodynamically unstable XC carbide layer on a formation substrate;
- decomposing the XC carbide layer into an X component and carbon;
- volatilizing the X component;
- forming a graphene layer from the carbon;
- forming a source region abutting the graphene layer;
- forming a drain region abutting the graphene layer;
- forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
- forming a gate abutting the gate dielectric;
- and
- wherein depositing the XC carbide layer on a formation substrate comprises depositing amorphous tin carbide on a (0001) hexagonal boron nitride substrate.
7 more elements
A method of forming a transistor comprising:
- depositing a thermodynamically unstable XC carbide layer on a formation substrate;
- decomposing the XC carbide layer into an X component and carbon;
- volatilizing the X component;
- forming a graphene layer from the carbon;
- forming a source region abutting the graphene layer;
- forming a drain region abutting the graphene layer;
- forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
- forming a gate abutting the gate dielectric;
- and
- wherein depositing the XC carbide layer on a formation substrate comprises depositing an epitaxial Ge0.95C0.05 layer on a (111) silicon carbide substrate.
7 more elements
A method of forming a transistor comprising:
- depositing a thermodynamically unstable XC carbide layer on a formation substrate comprising depositing magnesium carbide on a (111) silicon carbide substrate;
- decomposing the XC carbide layer into an X component and carbon;
- volatilizing the X component;
- forming a graphene layer from the carbon;
- forming a source region abutting the graphene layer;
- forming a drain region abutting the graphene layer;
- forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
- forming a gate abutting the gate dielectric;
- and
- wherein decomposing the XC carbide layer into an X component and carbon comprises heating the XC carbide layer to a temperature of about 400° C., wherein volatilizing the X component comprises heating to a temperature of about 600° C., and wherein forming the graphene layer comprises flash annealing at a temperature of about 850° C.
7 more elements
A method of fabricating a transistor comprising:
- providing a structural substrate comprising silicon;
- forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer;
- forming a graphene layer on the formation substrate, wherein forming the graphene layer comprises annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700-900° C. and forming the graphene layer by hydrocarbon chemical vapor deposition;
- forming a source region abutting the graphene layer;
- forming a drain region abutting the graphene layer;
- forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
- and
- forming a gate abutting the gate dielectric.
5 more elements
A method of fabricating a transistor comprising:
- providing a structural substrate comprising silicon;
- forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer;
- forming a graphene layer on the formation substrate, wherein forming the graphene layer comprises:
- annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700-900° C.;
- treating with a hydrogen gas plasma at temperatures of about 100-400° C. to selectively remove surface silicon from a silicon carbide layer outer surface and produce a hydrogen terminated carbon rich surface;
- and
- annealing at temperatures of about 850° C. or lower to desorb the hydrogen from the silicon carbide layer outer surface and form the graphene layer remaining carbon;
- forming a source region abutting the graphene layer;
- forming a drain region abutting the graphene layer;
- forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric;
- and
- forming a gate abutting the gate dielectric.
9 more elements
Dependencies are inferred from the claim text.