Method of manufacturing semiconductor package
AssigneeShinko Electric Industries Co., Ltd.
InventorsNoriyoshi Shimizu, Akio Rokugawa
Life of this patent
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Abstract
There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a pad is formed on the first surface; (b) disposing the semiconductor chip on a supporting substrate such that the first surface is directed upward; (c) forming an encapsulation resin layer on the supporting substrate so as to cover the semiconductor chip; and (d) polishing the encapsulation resin layer to expose a top surface of the pad.
Claims13
A method of manufacturing a semiconductor package, the method comprising:
- (a) providing a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a pad is formed on the first surface;
- (b) disposing the semiconductor chip on the supporting substrate through a fixing material such that the first surface is directed upward;
- (c) forming an encapsulation resin layer on the supporting substrate so as to cover the semiconductor chip;
- (d) polishing the encapsulation resin layer to expose a top surface of the pad;
- (e) forming an insulating layer on the encapsulation resin layer;
- (f) forming a wiring layer on the insulating layer, wherein the wiring layer includes a via connected to the pad and a wiring pattern, wherein step (e) and step (f) are alternately repeated;
- and
- (g) removing the supporting substrate and the fixing material,
- wherein the fixing material is a thermally removable adhesive agent, and step (g) includes heating the fixing material after step (f) until the supporting substrate and the fixing material separate from the semiconductor package.
A method of manufacturing a semiconductor package, the method comprising:
- (a) providing a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a pad is formed on the first surface;
- (b) disposing the semiconductor chip on a supporting substrate such that the first surface is directed upward;
- (c) forming an encapsulation resin layer on the supporting substrate so as to cover the semiconductor chip;
- (d) polishing the encapsulation resin layer to expose a top surface of the pad;
- (e) forming an insulating layer on the encapsulation resin layer;
- and
- (f) forming a wiring layer on the insulating layer, wherein the wiring layer includes a via connected to the pad and a wiring pattern,
- wherein
- step (e) and step (f) are alternately repeated,
- an uppermost wiring layer includes an external connection pad,
- the method further comprises forming a solder resist film on the uppermost wiring layer, the solder resist film formed to have an opening through which the external connection pad is exposed, and
- a sum of thickness of all wiring layers and all insulating layers and the solder resist film is smaller than that of the encapsulation resin layer.
Dependencies are inferred from the claim text.