Three dimensional microelectronic components and fabrication methods for same

A method of forming an electrical component, the method comprising:

• forming a first pattern of metal lines on a top surface of a substrate, each of the metal lines in the first pattern having a length;
• forming a second pattern of a metal lines one of a bottom surface of the substrate and a dielectric layer formed over the pattern of the first conductive material, the metal lines in the second pattern parallel to the metal lines in the first pattern;
• dicing the substrate into one or more die having a first diced surface and a second diced surface formed by the dicing of the substrate;
• and
• forming a third pattern of metal on the first diced surface;
• wherein forming the second pattern of a metal lines comprises forming the second pattern of metal lines horizontally displaced from the metal lines in the first pattern in a direction normal to a direction defined by the length of a metal line in the first pattern of metal lines and in a plane parallel to the bottom surface of the substrate.

A method of forming an electrical component, the method comprising:

• selecting a substrate;
• forming a layer of first sacrificial material on a top surface of the substrate;
• forming a pattern of a first conductive material on a top surface of the layer of the first sacrificial material;
• forming a layer of second sacrificial material on a top surface of the pattern of the first conductive material;
• forming a pattern of a second conductive material on a top surface of the layer of the second sacrificial material;
• forming an end structure physically joined to at least a portion of the pattern of the first conductive material and to at least a portion of the pattern of the second conductive material;
• removing the substrate and the layer of the first sacrificial material from the pattern of the first conductive material;
• embedding the pattern of the first conductive material and the pattern of the second conductive material in one of a reconstituted wafer and a multi-chip module;
• and
• removing the end structure from the embedded pattern of the first conductive material and pattern of the second conductive material.