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US 8,785,248 B2Granted
Wafer level packaging using a lead-frame
AssigneeMaxim Integrated Products, Inc.
InventorAhmad R. Ashrafzadeh
Life of this patent
Estimating the term…
Abstract
Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.
Claims37
A method of wafer level packaging comprising:
- a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof;
- b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer;
- c) electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer;
- etching the lead frame matrix to separate the lead frame contacts;
- d) dicing the first wafer.
2 more elements
A method of wafer level packaging comprising:
- a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof;
- b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer;
- c) electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer;
- attaching the lead frame matrix to a temporary substrate, etching the lead frame matrix to separate the lead frame contacts, then electrically connecting the lead frame contacts to the circuit contacts on the first wafer and removing the temporary substrate;
- d) dicing the first wafer.
2 more elements
A method of wafer level packaging comprising:
- a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof;
- b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer;
- c) electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer;
- coating the lead frame matrix with a polymer grinding the polymer to expose package contacts on the opposite side of the lead frame contacts before dicing;
- d) dicing the first wafer.
2 more elements
A method of wafer level packaging comprising:
- a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof;
- b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer;
- c) electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer;
- fabricating a second wafer having a matrix of second circuits thereon;
- thinning the second wafer;
- dicing the second wafer to form individual second circuits, each second circuit having an area that is less than the area of each first circuit;
- placing a second circuit on each of the first circuits and electrically connecting the first and second circuits;
- d) dicing the first wafer.
5 more elements
A method of wafer level packaging comprising:
- fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts on a first surface thereof;
- fabricating a second wafer having a matrix of second circuits thereon;
- thinning the second wafer;
- dicing the second wafer to form individual second circuits, each second circuit having an area that is less than the area of each first circuit;
- placing a second circuit on each of the first circuits and electrically connecting the first and second circuits;
- fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame contacts for electrically connecting to the circuit contacts on the first wafer in areas not occupied by the second circuits;
- electrically connecting the lead frame contacts on the lead frame matrix to the circuit contacts on the first wafer;
- coating the first and second circuits with a polymer, the polymer not covering package contacts on the lead frame matrix on a side opposite the lead frame contacts;
- and
- dicing the first wafer and lead frame matrix.
7 more elements
Dependencies are inferred from the claim text.