Semiconductor device with reduced potential between adjacent floating regions

A semiconductor device comprising:

• a plurality of floating regions arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween and include a first floating region and a second floating region located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate;
• an insulating layer interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate;
• and
• a capacitance forming portion extending either along and above the semiconductor substrate, or along a side of the row of the plurality of floating regions on the surface of the semiconductor substrate, or both, so that the capacitance forming portion is capacitively coupled to one or more of the plurality of floating regions, the one or more floating regions including the first floating region, wherein
• the capacitance forming portion forms a capacitance in parallel with, and in addition to, either a capacitance of the insulating region between the first floating region and the island region of the predetermined potential, or a capacitance of the insulating region between each adjacent pair of floating regions of the plurality of floating regions, or both,
• the capacitances between the capacitance forming portion and the floating regions decrease with increasing distance from the first floating region, and
• the capacitance forming portion includes an electrode provided on the semiconductor substrate and extending along and above the one or more floating regions so that the electrode is capacitively coupled to the one or more floating regions, such that the capacitive coupling of the electrode forms the capacitances between the capacitive forming portion and the floating regions.

A semiconductor device comprising:

• a plurality of floating regions arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween and include a first floating region and a second floating region located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate;
• an insulating layer interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate;
• and
• a capacitance forming portion extending either along and above the semiconductor substrate, or along a side of the row of the plurality of floating regions on the surface of the semiconductor substrate, or both, so that the capacitance forming portion is capacitively coupled to one or more of the plurality of floating regions, the one or more floating regions including the first floating region, wherein
• the capacitance forming portion forms a capacitance in parallel with, and in addition to, either a capacitance of the insulating region between the first floating region and the island region of the predetermined potential, or a capacitance of the insulating region between each adjacent pair of floating regions, or both,
• the capacitances between the capacitance forming portion and the floating regions decrease with increasing distance from the first floating region, and
• the capacitance forming portion includes a semiconductor region extending on the surface of the semiconductor substrate and along the row of the plurality of floating regions in such a manner that the semiconductor region extends along and adjacent to two or more of the plurality of floating regions with an insulating region between the semiconductor region and the two or more floating regions, such that a capacitive coupling of the semiconductor region with the one or more of the plurality of floating regions forms the capacitances between the capacitive forming portion and the floating regions.

A semiconductor device comprising:

• a plurality of floating regions arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween and include a first floating region and a second floating region located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate;
• an insulating layer interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate;
• a capacitance forming portion forming a capacitance in parallel with, and in addition to, either the capacitance of the insulating region between the first floating region and the island region of the predetermined potential, or the capacitance of the insulating region between each adjacent pair of floating regions of the plurality of floating regions, or both, the adjacent pair of floating regions including the first floating region;
• and
• a semiconductor element provided on the surface of the semiconductor device and adjacent to the plurality of floating regions with an insulating region between the semiconductor element and the plurality of floating regions, the semiconductor element having a first conductivity type region on a side adjacent to the first floating region and having a second conductivity type region on a side adjacent to the second floating region, wherein
• the capacitance forming portion includes a plurality of capacitive elements, and
• the capacitive elements on the side of the capacitance forming portion adjacent the first floating region have a greater capacitance than the capacitive elements on the side of the capacitance forming portion adjacent the second floating region.