Thin-film transistor, array substrate having the same and method of manufacturing the same

An array substrate comprising:

• a first conductive pattern comprising a first gate electrode formed on a substrate;
• a first gate insulation layer disposed on the first gate electrode;
• a semiconductor pattern formed on the first gate insulation layer and electrically insulated from the first gate electrode by the first gate insulation layer;
• a second gate insulation layer disposed on the semiconductor pattern;
• a second conductive pattern comprising a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode,
• wherein the second gate electrode is electrically insulated from the semiconductor pattern by the second gate insulation layer, and electrically insulated from the source electrode and the drain electrode by a first upper insulation layer;
• and
• a third conductive pattern comprising a pixel electrode electrically connected to the drain electrode,
• wherein the second conductive layer including the second gate electrode, the source electrode, and the drain electrode are formed of a same layer, and
• wherein each of the source electrode and the drain electrode is formed directly on respective opposite edge portions of the second gate insulation layer and the semiconductor pattern, and directly on portions of the first gate insulation layer.

A method of manufacturing a thin-film transistor, the method comprising:

• forming a first conductive layer on a substrate, wherein the first conductive layer comprises a first gate electrode;
• forming a first gate insulation layer on the first gate electrode;
• forming a semiconductor pattern on the first gate insulation layer;
• forming a second gate insulation layer on the semiconductor pattern;
• and
• forming a second conductive layer on the second gate insulation layer, wherein the second conductive layer comprises a source electrode, a drain electrode, and a second gate electrode,
• wherein the second conductive layer including the second gate electrode, the source electrode, and the drain electrode are formed of a same layer, and
• wherein each of the source electrode and the drain electrode is formed directly on respective opposite edge portions of the second gate insulation layer and the semiconductor pattern, and directly on portions of the first gate insulation layer.