MOSFET including asymmetric source and drain regions
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
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AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
Estimating the term…
At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.
A semiconductor structure comprising a field effect transistor, said field effect transistor including:
A semiconductor structure comprising a field effect transistor, said field effect transistor including:
A semiconductor structure comprising a field effect transistor, said field effect transistor including:
Dependencies are inferred from the claim text.