Transistors, semiconductor memory cells having a transistor and methods of forming the same

A transistor, comprising:

• a gate pattern on a semiconductor substrate, wherein the semiconductor substrate includes a base plate, an insulating layer and a semiconductor layer, sequentially stacked;
• at least one spacer pattern on each sidewall of the gate pattern;
• a gate insulating layer between the gate pattern and the semiconductor substrate;
• a dielectric layer on the gate insulating layer to cover the gate pattern and the at least one spacer pattern, wherein the dielectric layer includes an insulating material having silicon nitride that applies a tensile stress to the semiconductor layer;
• and
• a plurality of electrode terminals on both sides of the gate pattern and contacting the insulating layer through the dielectric layer, the gate insulating layer and the semiconductor layer, wherein the plurality of electrode terminals are in each in contact with one of the plurality of fourth semiconductor regions;
• a first semiconductor region under the gate pattern and having a first p-type impurity ion concentration;
• a plurality of second semiconductor regions each under one of the at least one spacer pattern, each of the plurality of second semiconductor regions having a second p-type impurity ion concentration being lower than the first p-type impurity ion concentration;
• a plurality of third semiconductor regions each adjacent to one of the plurality of second semiconductor regions, each of the plurality of third semiconductor regions having a first n-type impurity ion concentration;
• and
• a plurality of fourth semiconductor regions each adjacent to one of the at least one spacer pattern, wherein each of the plurality of fourth semiconductor regions has a second n-type impurity ion concentration,
• wherein the first, second, third and fourth semiconductor regions are electrically connected to one another and in the semiconductor substrate.

A semiconductor memory cell, comprising:

• a semiconductor substrate having an active region and a device isolation region, the device isolation region surrounding the active region, and the semiconductor substrate includes a base plate, an insulating layer and a semiconductor layer sequentially stacked;
• at least one gate pattern on the active region;
• a plurality of spacer patterns each on a sidewall of the at least one gate pattern;
• a gate insulating layer between the at least one gate pattern and the semiconductor substrate;
• a dielectric layer on the gate insulating layer to cover the at least one gate pattern and the plurality of spacer patterns, wherein the dielectric layer includes an insulating material having silicon nitride that applies a tensile stress to the semiconductor layer;
• a plurality of electrode terminals on both sides of the at least one gate pattern and contacting the insulating layer through the dielectric layer, the gate insulating layer and the semiconductor layer,
• a first semiconductor region in the active region under the at least one gate pattern and having a first p-type impurity ion concentration;
• a plurality of second semiconductor regions in the active region each under one of the plurality of spacer patterns, wherein each of the second semiconductor regions has a second p-type impurity ion concentration being lower than the first p-type impurity ion concentration;
• and
• a plurality of third semiconductor regions in the active region adjacent to the plurality of spacer patterns, wherein each of the plurality of third semiconductor regions has a first n-type impurity ion concentration,
• wherein the first, second and third semiconductor regions are electrically connected to one another, and in the semiconductor substrate, and
• wherein the plurality of electrode terminals are each in contact with one selected from the group consisting of the third semiconductor regions.