Partially depleted dielectric resurf LDMOS

A method of fabricating a semiconductor device, comprising in any order:

• forming a first doped well of a first conductivity type within a first lightly doped region, where the first doped well is disposed to surround a designated source region area and has a first lateral edge extending to a surface of a semiconductor substrate;
• forming in the designated source region area of the first doped well a first source region of a second, opposite, conductivity type;
• forming in the semiconductor substrate a second doped well of the second conductivity type having a second lateral edge extending to a surface of the semiconductor substrate and spaced apart from the first lateral edge, where second doped well is disposed to surround a designated drain region area, thereby forming a PN junction with first lightly doped substrate region at the surface of the semiconductor substrate;
• forming in the designated drain region area of the second doped well a first drain region of the second conductivity type;
• forming a plurality of insulator strips at the surface of the semiconductor substrate to define one or more narrow diode structures across the PN junction that extend between the first drain region and a designated gate electrode region;
• and
• forming a gate electrode overlying the surface of the semiconductor substrate at the designated gate electrode region.

A method for forming an LDMOS device, comprising:

• providing a semiconductor substrate having a first lightly doped p-type region extending to a surface of the semiconductor region in at least a first channel region;
• forming first and second wells in the semiconductor substrate spaced apart by at least the first lightly doped p-type region, where the first well is a p-type well for containing a source region and having a first lateral edge extending to a surface of the semiconductor substrate, and where the second well is an n-well for containing a drain region and having a second lateral edge extending to the surface of the semiconductor substrate;
• forming a plurality of insulator strips in an upper surface region of at least the second well to define one or more drain extension structures that extend from a designated drain region area to a designated gate electrode region area;
• forming a gate electrode insulated from the surface overlying the first lightly doped p-type region;
• using the gate electrode as at least a partial mask, implanting impurities into the semiconductor substrate to form a lightly doped n-type source extension region which overlaps with the first side edge of the gate electrode;
• and
• implanting n-type source and drain regions into the first and second wells, respectively, so that the source region is located within the first well to be spaced apart from the first lateral edge, and the drain region is located in the second well to be spaced apart from the second lateral edge.