LDMOS device with minority carrier shunt region

An electronic apparatus comprising:

• a substrate;
• and
• a transistor disposed in the substrate, the transistor comprising:
• first and second semiconductor regions having a first conductivity type;
• a third semiconductor region having a second conductivity type and in which a channel region is formed between the first and second semiconductor regions during operation;
• a fourth semiconductor region having the second conductivity type;
• wherein the fourth semiconductor region has a higher dopant concentration than the third semiconductor region to establish a shunt path for charge carriers of the second conductivity type, and wherein the shunt path electrically couples the third semiconductor region to a potential of the first semiconductor region.

A method of fabricating a transistor, the method comprising:

• forming a gate structure of the transistor on a semiconductor substrate;
• forming a well region in the semiconductor substrate, the well region extending under the gate structure via lateral diffusion where a channel region is formed during operation;
• forming a shunt region in the semiconductor substrate adjacent the well region;
• and
• forming a source region in the semiconductor substrate such that the shunt region is under the source region;
• wherein the shunt region has a higher dopant concentration than the well region to establish a shunt path that electrically couples the well region to a potential of the source region.