Embedded DRAM memory cell with additional patterning layer for improved strap formation

An embedded dynamic random access memory (eDRAM) device, comprising:

• a layered semiconductor structure, including:
• a buried insulating layer over a bulk layer;
• a semiconductor-on-insulator (SOI) layer over the buried insulating layer;
• and
• a dielectric layer over the SOI layer;
• a set of trenches located in the layered semiconductor structure and separated by a material stack of, from bottom to top, a bulk layer portion and a buried insulating layer portion, each trench including:
• an inner sidewall adjacent a section of the layered semiconductor structure between the trenches, the inner sidewall having a vertical portion of polysilicon extending only partially along the inner sidewall of each trench;
• and
• an outer sidewall opposite the inner sidewall, the outer sidewall having a second vertical portion of polysilicon extending along an entire depth of the outer sidewall, wherein said first vertical portion of polysilicon and said second vertical portion of polysilicon are components of a doped polysilicon structure, wherein said doped polysilicon structure includes a surface portion that is located beneath a top surface of said buried insulating portion;
• and
• a trench isolation structure having a first bottom surface portion in direct physical contact with said surface portion of said doped polysilicon structure that is located beneath said top surface of said buried insulating layer portion and a second bottom surface portion that is in direct contact with said top surface of said buried insulating layer portion.