Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a gate electrode level region having at least six adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, each gate electrode feature layout channel having a substantially equal length in the first direction, wherein each of the at least six adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,
• wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,
• wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,
• wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,
• wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
• wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature is separated from the third gate level feature by a first line end spacing as measured in the first direction,
• wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor of the second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature is separated from the fifth gate level feature by a second line end spacing as measured in the first direction,
• wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, and
• wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction;
• operating a computer to define a first gate contact defined to physically contact the first gate level feature;
• operating a computer to define a second gate contact defined to physically contact the second gate level feature;
• operating a computer to define a third gate contact defined to physically contact the third gate level feature;
• operating a computer to define a fourth gate contact defined to physically contact the fourth gate level feature;
• operating a computer to define a fifth gate contact defined to physically contact the fifth gate level feature;
• operating a computer to define a sixth gate contact defined to physically contact the sixth gate level feature,
• wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region,
• wherein each of the second, third, fourth, and fifth gate contacts is located over the inner portion of the gate electrode level region,
• wherein the third gate contact is offset in the first direction from the fourth gate contact;
• and
• operating a computer to define a plurality of interconnect level regions formed above the gate electrode level region;
• and
• operating a computer to define a first electrical connection to electrically connect the second gate level feature to the fifth gate level feature, the first electrical connection defined to extend through only one interconnect level region of the plurality of interconnect level regions, the first electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the first electrical connection within the one interconnect level region is linear-shaped.

A computer readable medium having program instructions stored thereon for generating a layout of an integrated circuit, comprising:

• program instructions for defining a gate electrode level region having at least six adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, each gate electrode feature layout channel having a substantially equal length in the first direction, wherein each of the at least six adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,
• wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,
• wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,
• wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,
• wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
• wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature is separated from the third gate level feature by a first line end spacing as measured in the first direction,
• wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor of the second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature is separated from the fifth gate level feature by a second line end spacing as measured in the first direction,
• wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, and
• wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction;
• program instructions for defining a first gate contact defined to physically contact the first gate level feature;
• program instructions for defining a second gate contact defined to physically contact the second gate level feature;
• program instructions for defining a third gate contact defined to physically contact the third gate level feature;
• program instructions for defining a fourth gate contact defined to physically contact the fourth gate level feature;
• program instructions for defining a fifth gate contact defined to physically contact the fifth gate level feature;
• program instructions for defining a sixth gate contact defined to physically contact the sixth gate level feature,
• wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region,
• wherein each of the second, third, fourth, and fifth gate contacts is located over the inner portion of the gate electrode level region,
• wherein the third gate contact is offset in the first direction from the fourth gate contact;
• and
• program instructions for defining a plurality of interconnect level regions formed above the gate electrode level region;
• and
• program instructions for defining a first electrical connection to electrically connect the second gate level feature to the fifth gate level feature, the first electrical connection defined to extend through only one interconnect level region of the plurality of interconnect level regions, the first electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the first electrical connection within the one interconnect level region is linear-shaped.