III-nitride growth method on silicon substrate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Ming Chen, Po-Chun Liu, Hung-Ta Lin, Chin-Cheng Chang, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
Life of this patent
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Abstract
A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer.
Claims22
A circuit structure comprising:
- a silicon substrate;
- a patterned dielectric layer over and in direct contact with a top surface of the silicon substrate, the patterned dielectric layer comprising a plurality of vias through the dielectric layer;
- a vertical growth layer disposed over the substrate and within the vias in the patterned dielectric layer;
- a lateral growth layer of group-III to group-V (III-V) compound semiconductor layer disposed over the vertical growth layer and the patterned dielectric layer, forming a continuous layer over the patterned dielectric layer and the vertical growth layer;
- and
- a graded group III-V superlattice layer over the lateral growth layer.
A circuit structure comprising:
- a silicon substrate;
- a patterned dielectric layer over and in direct contact with a top surface of the silicon substrate, the patterned dielectric layer comprising a plurality of vias through the dielectric layer, said plurality of vias arranged in a hexagonal pattern;
- a vertical growth layer disposed over the substrate and within the vias in the patterned dielectric layer;
- a lateral growth layer of group-III to group-V (III-V) compound semiconductor layer disposed over the vertical growth layer and the patterned dielectric layer, forming a continuous layer over the patterned dielectric layer and the vertical growth layer;
- a graded group III-V superlattice layer over the lateral growth layer;
- and
- a bulk layer of group III-V compound semiconductor layer over the lateral growth layer.
A high electron mobility transistor comprising:
- a silicon substrate;
- a patterned dielectric layer over and directly contacting a top surface of the silicon substrate, the patterned dielectric layer comprising a plurality of vias through the dielectric layer, said plurality of vias each having hexagonal openings;
- a vertical growth layer disposed over the substrate and within the vias in the patterned dielectric layer;
- a lateral growth layer of group-III to group-V (III-V) compound semiconductor layer disposed over the vertical growth layer and the patterned dielectric layer, forming a continuous layer over the patterned dielectric layer and the vertical growth layer;
- a graded group III-V superlattice layer over the lateral growth layer;
- and
- a bulk layer of group III-V compound semiconductor layer over the lateral growth layer.
Dependencies are inferred from the claim text.