Array substrate structure of display panel and method of making the same

An array substrate structure of a display panel comprising:

• a substrate having a wiring region and a display region defined thereon;
• a first patterned conductive layer disposed on the substrate and comprising a plurality of gate lines and gate electrodes disposed in the display region and a plurality of first gate tracking lines electrically connected to a portion of the gate lines;
• a plurality of first wirings disposed in the wiring region;
• a first patterned insulating layer disposed on the first wirings, wherein the first patterned insulating layer further has a plurality of first contact holes respectively exposing a portion of the gate lines;
• a plurality of second wirings disposed on the first patterned insulating layer;
• a second patterned conductive layer disposed on the first patterned insulating layer and comprising a plurality of data lines, a plurality of source electrodes and a plurality of drain electrodes disposed in the display region and a plurality of second gate tracking lines electrically connected to the exposed portions of the gate lines through the first contact holes;
• a patterned semiconductor layer disposed on the second patterned conductive layer and comprising a plurality first protective patterns disposed in the wiring region and respectively disposed on corresponding second wirings, and a plurality of semiconductor channel layers disposed in the display region and respectively disposed on the corresponding gate electrodes, each of the first protective patterns comprising a semiconductor material;
• a second patterned insulating layer disposed on the patterned semiconductor layer and comprising a plurality of second protective patterns disposed in the wiring region and respectively disposed on the corresponding first protective patterns, and a plurality of channel protective layers disposed in the display region and disposed on the corresponding semiconductor channel layers, each of the second protective patterns comprising an inorganic insulating material;
• a first patterned protective layer disposed on the second patterned insulating layer;
• a second patterned protective layer disposed on the first patterned protective layer, wherein the first patterned protective layer and the second patterned protective layer expose each of the second protective patterns, and the first patterned protective layer and the second patterned protective layer have a plurality of second contact holes respectively exposing the drain electrodes;
• a first patterned transparent conductive layer disposed on the second patterned protective layer;
• a third patterned protective layer disposed on the first patterned transparent conductive layer;
• and
• a second patterned transparent conductive layer disposed on the third patterned protective layer;
• wherein the first wirings comprise the first gate tracking lines, and the second wirings comprise the second gate tracking lines.